公开(公告)号：US11270978B2

公开(公告)日：2022-03-08

申请号：US16713239

申请日：2019-12-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Fa Lu ,  Cheng-Yuan Tsai ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L23/48 ,  H01L27/06 ,  H01L21/822 ,  H01L23/29 ,  H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L25/00

摘要： A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer.

公开(公告)号：US11114378B2

公开(公告)日：2021-09-07

申请号：US16389500

申请日：2019-04-19

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Chen-Fa Lu ,  Cheng-Yuan Tsai ,  Ching-Chung Hsu ,  Chung-Long Chang

IPC分类号： H01L29/00 ,  H01L23/522 ,  H01L23/532 ,  H01L21/027 ,  H01L21/288 ,  H01L21/311 ,  H01L21/768 ,  H01L23/31 ,  H01L23/528

摘要： The present disclosure provides a semiconductor structure having an ultra thick metal (UTM). The semiconductor structure includes a substrate, a metal layer over the substrate, and an UTM over the metal layer. An area density of the UTM is greater than 40% and a thickness of the UTM is equal to or greater than 6 micrometer. The present disclosure provides a method for manufacturing a semiconductor structure having a UTM. The method includes patterning a dielectric layer with a plurality of trenches by a first mask, patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, and selectively plating conductive materials in the plurality of trenches.

公开(公告)号：US20160049384A1

公开(公告)日：2016-02-18

申请号：US14459144

申请日：2014-08-13

申请人： Taiwan Semiconductor Manufacturing Company Ltd.

发明人： Chen-Fa Lu ,  Cheng-Yuan Tsai ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

IPC分类号： H01L25/065 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L25/00 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/13 ,  H01L24/80 ,  H01L24/89 ,  H01L25/50 ,  H01L27/0688 ,  H01L2224/023 ,  H01L2224/02351 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2225/06548 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82 ,  H01L2924/01074

摘要： A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer.

摘要翻译： 结构包括第一和第二衬底，第一和第二应力缓冲层以及后钝化互连（PPI）结构。 第一和第二衬底分别包括第一和第二半导体衬底以及第一和第二半导体衬底上的第一和第二互连结构。 第二互连结构位于第二半导体衬底的第一侧上。 第一衬底在接合界面处结合到第二衬底。 通孔至少通过第二半导体衬底延伸到第二互连结构中。 第一应力缓冲层位于与第二半导体衬底的第一侧相反的第二半导体衬底的第二侧上。 PPI结构位于第一应力缓冲层上，并电连接到通孔。 第二应力缓冲层位于PPI结构和第一应力缓冲层上。

公开(公告)号：US20170200640A1

公开(公告)日：2017-07-13

申请号：US14993468

申请日：2016-01-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Shih-Pei Chou ,  Chen-Fa Lu ,  Jiech-Fun Lu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

IPC分类号： H01L21/768 ,  H01L21/033 ,  H01L23/522 ,  H01L21/32 ,  H01L21/762 ,  H01L23/532

CPC分类号： H01L21/0332 ,  H01L21/32 ,  H01L21/76224 ,  H01L21/76807 ,  H01L21/76898 ,  H01L23/481

摘要： A semiconductor structure comprises a substrate comprising an interlayer dielectric (ILD) and a silicon layer disposed over the ILD, wherein the ILD comprises a conductive structure disposed therein, a dielectric layer disposed over the silicon layer, and a conductive plug electrically connected with the conductive structure and extended from the dielectric layer through the silicon layer to the ILD, wherein the conductive plug has a length running from the dielectric layer to the ILD and a width substantially consistent along the length.

公开(公告)号：US20140131861A1

公开(公告)日：2014-05-15

申请号：US14096435

申请日：2013-12-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Fa Lu ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Wei-Yu Chen ,  Cheng-Ting Chen

IPC分类号： H01L23/00

CPC分类号： H01L24/13 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0362 ,  H01L2224/03831 ,  H01L2224/03901 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/1147 ,  H01L2224/11622 ,  H01L2224/1181 ,  H01L2224/1183 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/93 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H05K3/28 ,  H05K3/3478 ,  H05K3/4007 ,  H01L2224/11 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/1082

摘要： A semiconductor device having a polymer layer and a method of fabricating the same is provided. A two-step plasma treatment for a surface of the polymer layer includes a first plasma process to roughen the surface of the polymer layer and loosen contaminants, and a second plasma process to make the polymer layer smoother or make the polymer layer less rough. An etch process may be used between the first plasma process and the second plasma process to remove the contaminants loosened by the first plasma process. In an embodiment, the polymer layer exhibits a surface roughness between about 1% and about 8% as measured by Atomic Force Microscopy (AFM) with the index of surface area difference percentage (SADP) and/or has surface contaminants of less than about 1% of Ti, less than about 1% of F, less than about 1.5% Sn, and less than about 0.4% of Pb.

摘要翻译： 提供了具有聚合物层的半导体器件及其制造方法。 用于聚合物层表面的两步等离子体处理包括使聚合物层的表面粗糙化并且使污染物松动的第一等离子体工艺，以及使聚合物层更平滑或使聚合物层变得粗糙的第二等离子体工艺。 可以在第一等离子体工艺和第二等离子体工艺之间使用蚀刻工艺，以除去由第一等离子体工艺松动的污染物。 在一个实施方案中，聚合物层通过原子力显微镜（AFM）测量的表面粗糙度在约1％至约8％之间，其表面积差异百分比（SADP）指数和/或具有小于约1的表面污染物 的Ti％，小于约1％的F，小于约1.5％的Sn和小于约0.4％的Pb。

公开(公告)号：US10534353B2

公开(公告)日：2020-01-14

申请号：US14045440

申请日：2013-10-03

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chen-Fa Lu ,  Cheng-Ting Chen ,  James Hu ,  Chung-Shi Liu

IPC分类号： G05B19/418

摘要： A system for reducing processing defects during processing of a semiconductor wafer prior to back-grinding the wafer includes a table having one or more holes formed therein, wherein the table comprises at least one of a chuck table or a support table, wherein the holes are perpendicular to the surface upon which a pre-back-grinding (PBG) process occurs. The system further includes one or more sensors disposed in said holes for monitoring a parameter during the PBG process. The system further includes a computer-implemented process control tool coupled with the one or more sensors and configured to determine whether the PBG process will continue.

公开(公告)号：US10269701B2

公开(公告)日：2019-04-23

申请号：US14874147

申请日：2015-10-02

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Chen-Fa Lu ,  Cheng-Yuan Tsai ,  Ching-Chung Hsu ,  Chung-Long Chang

IPC分类号： H01L29/00 ,  H01L23/522 ,  H01L21/027 ,  H01L21/288 ,  H01L21/311 ,  H01L21/768 ,  H01L23/31 ,  H01L23/528 ,  H01L23/532

摘要： The present disclosure provides a semiconductor structure having an ultra thick metal (UTM). The semiconductor structure includes a substrate, a metal layer over the substrate, and an UTM over the metal layer. An area density of the UTM is greater than 40% and a thickness of the UTM is equal to or greater than 6 micrometer. The present disclosure provides a method for manufacturing a semiconductor structure having a UTM. The method includes patterning a dielectric layer with a plurality of trenches by a first mask, patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, and selectively plating conductive materials in the plurality of trenches.

公开(公告)号：US10128113B2

公开(公告)日：2018-11-13

申请号：US14993468

申请日：2016-01-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Shih-Pei Chou ,  Chen-Fa Lu ,  Jiech-Fun Lu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

IPC分类号： H01L21/033 ,  H01L21/762 ,  H01L21/32 ,  H01L21/768 ,  H01L23/48

摘要： A semiconductor structure comprises a substrate comprising an interlayer dielectric (ILD) and a silicon layer disposed over the ILD, wherein the ILD comprises a conductive structure disposed therein, a dielectric layer disposed over the silicon layer, and a conductive plug electrically connected with the conductive structure and extended from the dielectric layer through the silicon layer to the ILD, wherein the conductive plug has a length running from the dielectric layer to the ILD and a width substantially consistent along the length.

公开(公告)号：US09508659B2

公开(公告)日：2016-11-29

申请号：US13932765

申请日：2013-07-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Fa Lu ,  Yeur-Luen Tu ,  Shu-Ju Tsai ,  Cheng-Ta Wu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC分类号： H01L21/687 ,  H01L23/00 ,  H01L21/304 ,  H01L21/67

CPC分类号： H01L23/562 ,  H01L21/2007 ,  H01L21/304 ,  H01L21/67092 ,  H01L21/6715 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method includes holding bonded wafers by a wafer holding module. A gap between the bonded wafers along an edge is filled with a protection material.

摘要翻译： 一种方法包括通过晶片保持模块保持接合晶片。 沿着边缘的接合晶片之间的间隙填充有保护材料。

公开(公告)号：US20150001681A1

公开(公告)日：2015-01-01

申请号：US13932765

申请日：2013-07-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Fa Lu ,  Yeur-Luen Tu ,  Shu-Ju Tsai ,  Cheng-Ta Wu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC分类号： H01L21/02 ,  H01L23/00

CPC分类号： H01L23/562 ,  H01L21/2007 ,  H01L21/304 ,  H01L21/67092 ,  H01L21/6715 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method includes holding bonded wafers by a wafer holding module. A gap between the bonded wafers along an edge is filled with a protection material.

摘要翻译： 一种方法包括通过晶片保持模块保持接合晶片。 沿着边缘的接合晶片之间的间隙填充有保护材料。