公开(公告)号：US20100109702A1

公开(公告)日：2010-05-06

申请号：US12645784

申请日：2009-12-23

申请人： Takeshi Sakata ,  Kiyoo Itoh ,  Masashi Horiguchi

发明人： Takeshi Sakata ,  Kiyoo Itoh ,  Masashi Horiguchi

IPC分类号： H03K19/003 ,  G05F1/10

CPC分类号： H03K19/0016 ,  G11C5/147 ,  G11C7/065 ,  G11C8/08 ,  G11C8/12 ,  H03K19/00361

摘要： A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed.

摘要翻译： 包括第一和第二电力线的半导体器件，以及耦合在电力线之间的第一和第二电路块。 第一开关元件插入在第一电路块和至少一个电源线之间，并且第二开关元件插入在第二电路块和至少一个电源线之间。 第一开关元件被导通以允许第一电路块通过第一和第二电力线接收电力电压，而第二开关元件变得不导通，以防止第二电路块通过第一和第二电力接收电力电压 使得流过第二电路的漏电流被抑制。

公开(公告)号：US07379328B2

公开(公告)日：2008-05-27

申请号：US11812641

申请日：2007-06-20

申请人： Kenichi Osada ,  Kiyoo Itoh

发明人： Kenichi Osada ,  Kiyoo Itoh

IPC分类号： G11C11/00 ,  G11C5/06 ,  G11C7/02 ,  G11C8/00

CPC分类号： H01L27/24 ,  G11C7/04 ,  G11C13/0004

摘要： Memory blocks having memory cells which are comprised of vertical transistors and memory elements in which the resistance value is varied depending on the temperature imposed on the upper side thereof, are laminated to realize a highly-integrated non-volatile memory.

摘要翻译： 具有由垂直晶体管构成的存储单元和其中电阻值根据其上侧施加的温度而变化的存储单元的存储器块被层叠以实现高度集成的非易失性存储器。

公开(公告)号：US20060203542A1

公开(公告)日：2006-09-14

申请号：US11341385

申请日：2006-01-30

申请人： Kenzo Kurotsuchi ,  Kiyoo Itoh ,  Norikatsu Takaura ,  Kenichi Osada

发明人： Kenzo Kurotsuchi ,  Kiyoo Itoh ,  Norikatsu Takaura ,  Kenichi Osada

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C2013/0047 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/79

摘要： A semiconductor non volatile memory device capable of multiple write operations with high reliability is implemented. The memory device includes memory cells, each comprising a first electrode, a second electrode, and an information storage section put between the two electrodes, wherein an operation to feed a first pulse current from the first electrode to the second, and another operation to feed a second pulse current from the second electrode to the first. A segregation of composing elements of the information storage section is caused by applying the first pulse, however, the segregation of elements is resolved by applying the second pulse, and the composition of the element recovers to the original state.

摘要翻译： 实现了具有高可靠性的多次写入操作的半导体非易失性存储器件。 存储器件包括存储单元，每个存储单元包括放置在两个电极之间的第一电极，第二电极和信息存储部分，其中将第一脉冲电流从第一电极馈送到第二电极的操作，以及另一个进给 从第二电极到第一电极的第二脉冲电流。 信息存储部分的组合元件的分离是通过施加第一脉冲引起的，然而，通过应用第二脉冲来解决元件的偏析，并且元件的组成恢复到原始状态。

公开(公告)号：US20060148135A1

公开(公告)日：2006-07-06

申请号：US11368603

申请日：2006-03-07

申请人： Hideyuki Matsuoka ,  Kiyoo Itoh ,  Motoyasu Terao ,  Satoru Hanzawa ,  Takeshi Sakata

发明人： Hideyuki Matsuoka ,  Kiyoo Itoh ,  Motoyasu Terao ,  Satoru Hanzawa ,  Takeshi Sakata

IPC分类号： H01L21/50

CPC分类号： H01L27/2454 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.

公开(公告)号：US07023721B2

公开(公告)日：2006-04-04

申请号：US11085213

申请日：2005-03-22

申请人： Kiyoo Itoh ,  Kazuo Nakazato

发明人： Kiyoo Itoh ,  Kazuo Nakazato

IPC分类号： G11C11/24

CPC分类号： G11C11/4076 ,  G11C11/404 ,  G11C11/405 ,  G11C16/0408 ,  G11C2207/2281 ,  G11C2207/229

摘要： A semiconductor integrated circuit device including a plurality of memory cells, each having a storage MOSFET holding information in a gate of the storage MOSFET, a write transistor supplying a write information voltage corresponding to the information to the gate storage MOSFET, and a capacitor having first and second terminals. Word lines and data lines are coupled with the memory cells. The first capacitor terminal is coupled with one of the word lines and the second capacitor terminal is coupled with the gate of the storage MOSFET. In a read operation of the semiconductor integrated circuit device, the gate voltage of the storage MOSFET is boosted by a transition of the word line from a first voltage to a second voltage greater than the first voltage.

摘要翻译： 一种半导体集成电路装置，包括多个存储单元，每个存储单元具有保存在存储MOSFET的栅极中的信息的存储MOSFET;写入晶体管，其将与该信息相对应的写入信息电压提供给栅极存储MOSFET;以及电容器，其具有第一 和第二终端。 字线和数据线与存储器单元耦合。 第一电容器端子与字线之一耦合，第二电容器端子与存储MOSFET的栅极耦合。 在半导体集成电路器件的读取操作中，通过字线从第一电压到大于第一电压的第二电压的转变来提高存储MOSFET的栅极电压。

公开(公告)号：US20050045933A1

公开(公告)日：2005-03-03

申请号：US10914223

申请日：2004-08-10

申请人： Shinichiro Kimura ,  Toshiaki Yamanaka ,  Kiyoo Itoh ,  Takeshi Sakata ,  Tomonori Sekiguchi ,  Hideyuki Matsuoka

发明人： Shinichiro Kimura ,  Toshiaki Yamanaka ,  Kiyoo Itoh ,  Takeshi Sakata ,  Tomonori Sekiguchi ,  Hideyuki Matsuoka

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/108 ,  H01L27/115 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10852 ,  H01L27/108 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/90

摘要： A capacitor consisting of a storage electrode (19), a capacitor dielectric film (20) and a plate electrode (21) is formed in a trench formed through dielectric films (6, 8, 10 and 12) stacked on a semiconductor substrate (1) and buried wiring layers (9 and 11) are formed under the capacitor. As the capacitor is formed not in the semiconductor substrate but over it, there is room in area in which the capacitor can be formed and the difficultly of forming wiring is reduced by using the wiring layers (9 and 11) for a global word line and a selector line. As the upper face of an dielectric film (32) which is in contact with the lower face of wiring (34) in a peripheral circuit area is extended into a memory cell area and is in contact with the side of the capacitor (33), step height between the peripheral circuit area and the memory cell area is remarkably reduced.

摘要翻译： 在由半导体衬底（1）上层叠的电介质膜（6,8,10和12）形成的沟槽中形成由存储电极（19），电容器电介质膜（20）和平板电极（21）构成的电容器 ）和埋入布线层（9和11）形成在电容器下面。 由于电容器不是形成在半导体衬底中而是在其上形成，所以存在可以形成电容器的区域的空间，并且通过使用全局字线的布线层（9和11）难以形成布线， 选择线。 由于在周边电路区域与布线（34）的下表面接触的电介质膜（32）的上表面延伸到存储单元区域并与电容器（33）的一侧接触， 外围电路区域和存储单元区域之间的台阶高度显着降低。

公开(公告)号：US06838901B2

公开(公告)日：2005-01-04

申请号：US10626532

申请日：2003-07-25

申请人： Takeshi Sakata ,  Kiyoo Itoh ,  Masashi Horiguchi

发明人： Takeshi Sakata ,  Kiyoo Itoh ,  Masashi Horiguchi

IPC分类号： G11C5/14 ,  G11C7/06 ,  G11C8/08 ,  G11C8/12 ,  H03K19/00 ,  H03K19/003 ,  H03K17/16 ,  H03K19/017

CPC分类号： G11C8/18 ,  G11C5/147 ,  G11C7/065 ,  G11C8/08 ,  G11C8/12 ,  G11C11/4074 ,  H03K19/0016 ,  H03K19/0027 ,  H03K19/00361

摘要： Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element in their off-state is smaller than the subthreshold current of MOS transistors within the corresponding circuit block. Active current is supplied to active circuit blocks, while switching elements of non-active circuit blocks are turned off. Thus, dissipation currents of non-active circuit blocks are limited to leakage current value of corresponding switching elements. Thus, the sum of dissipation currents of non-active circuit blocks is made smaller than the active current in the active circuit blocks. As a result, power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.

摘要翻译： 半导体集成电路芯片的功耗在2.5V或更低的工作电压下工作时，功耗降低。 开关元件设置在芯片内的每个电路块中。 开关元件的常数被设定为使得其断开状态下的每个开关元件中的漏电流小于相应电路块内的MOS晶体管的亚阈值电流。 有源电流被提供给有源电路块，而非有效电路块的开关元件被关断。 因此，非有源电路块的耗散电流被限制为相应的开关元件的漏电流值。 因此，非有源电路块的耗散电流的总和小于有源电路块中的有功电流。 结果，即使在活动状态下，半导体集成电路芯片的功率消耗也可以减小。

公开(公告)号：US06754114B2

公开(公告)日：2004-06-22

申请号：US10401975

申请日：2003-03-31

申请人： Masashi Horiguchi ,  Jun Etoh ,  Masakazu Aoki ,  Kiyoo Itoh

发明人： Masashi Horiguchi ,  Jun Etoh ,  Masakazu Aoki ,  Kiyoo Itoh

IPC分类号： G11C700

CPC分类号： G11C29/80 ,  G11C29/785 ,  G11C29/808

摘要： A semiconductor memory is provided with a defect recovery scheme featuring a redundancy circuit. The memory array in the memory has a plurality of word lines, a plurality of bit lines, a spare bit line, and a plurality of memory cells. The redundancy circuit includes one or more comparing circuits having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. Each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected.

摘要翻译： 半导体存储器具有冗余电路的缺陷恢复方案。 存储器中的存储器阵列具有多个字线，多个位线，备用位线和多个存储器单元。 冗余电路包括具有可编程元件的一个或多个比较电路，其作为用于在其中存储存在于存储器阵列中的缺陷地址的存储器。 冗余电路的可编程元件可以根据多种不同类型的缺陷模式中的任何一种进行编程。 冗余电路的每个比较电路将在其中输入的信息（数据），例如可能在地址多路复用系统的控制下的列和行地址与在比较电路的可编程元件中编程的信息（数据）进行比较。 在此比较的基础上，进行适当的缺陷恢复。

公开(公告)号：US06753568B1

公开(公告)日：2004-06-22

申请号：US09362200

申请日：1999-07-28

申请人： Kazuo Nakazato ,  Kiyoo Itoh ,  Hiroshi Mizuta ,  Toshihiko Sato ,  Toshikazu Shimada ,  Haroon Ahmed

发明人： Kazuo Nakazato ,  Kiyoo Itoh ,  Hiroshi Mizuta ,  Toshihiko Sato ,  Toshikazu Shimada ,  Haroon Ahmed

IPC分类号： H01L2976

CPC分类号： H01L21/28185 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/02 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/772 ,  H01L29/78642 ,  H01L29/7883 ,  H01L29/7888

摘要： A memory device includes a memory node (1) to which charge is written through a tunnel barrier configuration (2) from a control electrode (9). The stored charge effects the conductivity of a source/drain path (4) and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier configuration, which may comprise alternating layers (16) of polysilicon of 3 nm thickness and layers (15) of Si3N4 of 1 nm thickness, overlying polycrystalline layer of silicon (1) which forms the memory node. Alternative barrier configurations (2) are described, including a Schottky barrier configuration, and conductive nanometer scale conductive islands (30, 36, 44), which act as the memory node, distributed in an electrically insulating matrix.

摘要翻译： 存储器件包括从控制电极（9）通过隧道势垒配置（2）写入电荷的存储器节点（1）。 存储的电荷影响源/漏路径（4）的电导率，并且通过监测路径的电导率来读取数据。 电荷势垒配置包括多隧道势垒结构，其可以包括3nm厚度的多晶硅的交替层（16）和1nm厚度的Si 3 N 4层（15），覆盖形成存储器节点的硅的多晶层（1） 。 描述了包括肖特基势垒结构的替代屏障配置（2）和用作存储节点的导电纳米级导电岛（30,36,44），其分布在电绝缘矩阵中。

公开(公告)号：US06614696B2

公开(公告)日：2003-09-02

申请号：US10325920

申请日：2002-12-23

申请人： Yusuke Kanno ,  Kiyoo Itoh

发明人： Yusuke Kanno ,  Kiyoo Itoh

IPC分类号： G11C1134

CPC分类号： G11C7/18 ,  G11C11/405 ,  G11C11/4097

摘要： A semiconductor integrated circuit is disclosed, in which a memory is activated at high speed in commensurate with a high-speed logic circuit mounted with the memory in order to reduce the cost using a DRAM of a 3-transistor cell requiring no capacitor. A pair of data lines connected with a plurality of memory cells having the amplification function are set to different precharge voltage values, thereby eliminating the need of a dummy cell. The elimination of the need of the dummy cell unlike in the conventional DRAM circuit using a gain cell reduces both the required space and the production cost. A hierarchical structure of the data lines makes a high-speed operation possible. Also, a DRAM circuit can be fabricated through a fabrication process matched with an ordinary logic element.

摘要翻译： 公开了一种半导体集成电路，其中存储器以与安装有存储器的高速逻辑电路相当的高速度被激活，以便使用不需要电容器的3晶体管单元的DRAM来降低成本。 与具有放大功能的多个存储单元连接的一对数据线被设置为不同的预充电电压值，从而不需要虚设单元。 与使用增益单元的常规DRAM电路不同，消除虚设电池的需要减少了所需的空间和生产成本。 数据线的层次结构使得高速操作成为可能。 此外，可以通过与普通逻辑元件匹配的制造工艺来制造DRAM电路。