公开(公告)号：US20070290394A1

公开(公告)日：2007-12-20

申请号：US11425210

申请日：2006-06-20

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger

IPC分类号： B28B1/48

CPC分类号： H01L21/02164 ,  H01L21/0228 ,  H01L21/31608 ,  H01L21/32051 ,  H01L21/76801 ,  H01L21/76838 ,  H01L21/7684 ,  H01L23/53276 ,  H01L2924/0002 ,  Y10T428/249924 ,  H01L2924/00

摘要： A method for forming a self-planarizing wiring layer for a semiconductor device includes forming a mat of filament material over a semiconductor substrate, and infusing the mat with a conductive material formed at a thickness substantially corresponding to the thickness of the mat of filament material. The mat is then patterned so as to expose regions where conductive wiring is not to be present, and the infused conductive material is removed from the exposed regions. The exposed regions of the mat are infused with an insulating material, formed at a thickness substantially corresponding to the thickness of the mat of filament material.

摘要翻译： 用于形成半导体器件的自平面化布线层的方法包括在半导体衬底上形成丝状材料垫，并且以基本上对应于长丝材料垫的厚度的厚度形成的导电材料注入垫。 然后将垫图案化以暴露不存在导电布线的区域，并且从暴露区域去除输入的导电材料。 衬垫的暴露区域注入绝缘材料，绝缘材料以基本上对应于长丝材料垫的厚度的厚度形成。

公开(公告)号：US07227233B2

公开(公告)日：2007-06-05

申请号：US11162472

申请日：2005-09-12

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Jack A. Mandelman

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Jack A. Mandelman

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L27/1203 ,  H01L27/1021 ,  H01L27/112 ,  H01L27/11213

摘要： A silicon-on-insulator (SOI) Read Only Memory (ROM), and a method of making the SOI ROM. ROM cells are located at the intersections of stripes in the surface SOI layer with orthogonally oriented wires on a conductor layer. Contacts from the wires connect to ROM cell diodes in the upper surface of the stripes. ROM cell personalization is the presence or absence of a diode and/or contact.

摘要翻译： 绝缘体上硅（SOI）只读存储器（ROM）以及制造SOI ROM的方法。 ROM单元位于导体层上的表面SOI层中的条纹与正交取向的导线之间的交叉处。 电线的触点连接到条纹上表面的ROM单元二极管。 ROM单元个性化是存在或不存在二极管和/或接触。

公开(公告)号：US07087531B1

公开(公告)日：2006-08-08

申请号：US10905681

申请日：2005-01-17

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L29/72

CPC分类号： H01L21/02164 ,  H01L21/0214 ,  H01L21/02282 ,  H01L21/3143 ,  H01L21/3147 ,  H01L21/316 ,  H01L21/76224 ,  H01L21/823878

摘要： A method and structure for forming a semiconductor structure. A semiconductor substrate is provided. A trench is formed within the semiconductor substrate. A first layer of electrically insulative material is formed within the trench. A first portion and a second portion of the first layer of electrically insulative material is removed. A second layer of electrically insulative material is selectively grown on the first layer comprising the removed first portion and the removed second portion.

公开(公告)号：US06989323B2

公开(公告)日：2006-01-24

申请号：US10709314

申请日：2004-04-28

申请人： Bruce B. Doris ,  Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Bruce B. Doris ,  Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/823437 ,  H01L21/28097 ,  H01L21/28123 ,  H01L21/32139 ,  H01L29/4975

摘要： A method for forming a gate structure for a semiconductor device includes defining a conductive sacrificial structure on a substrate, forming a reacted metal film on sidewalls of the conductive sacrificial structure, and removing unreacted portions of the conductive sacrificial structure.

摘要翻译： 用于形成半导体器件的栅极结构的方法包括在衬底上限定导电牺牲结构，在导电牺牲结构的侧壁上形成反应的金属膜，以及去除导电牺牲结构的未反应部分。

公开(公告)号：US06489207B2

公开(公告)日：2002-12-03

申请号：US09871926

申请日：2001-06-01

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/223 ,  H01L21/2236 ,  H01L21/28035 ,  H01L21/28061 ,  H01L21/32 ,  H01L21/823814 ,  H01L21/823842

摘要： The present invention relates to a method of forming a very shallow source-drain (S/D) extension while simultaneously highly doping a very narrow polysilicon gate through to the gate dielectric interface. The invention also relates to the resulting semiconductor.

公开(公告)号：US06452265B1

公开(公告)日：2002-09-17

申请号：US09493929

申请日：2000-01-28

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Rosemary A. Previti-Kelly ,  Edmund Sprogis

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Rosemary A. Previti-Kelly ,  Edmund Sprogis

IPC分类号： H01L2334

CPC分类号： H01L21/568 ,  H01L21/6835 ,  H01L23/3738 ,  H01L23/5389 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2224/0401

摘要： A multi-chip module is constructed by aligning prewired chips on a support wafer and depositing a nonconductive thermally conductive and electrically nonconductive material having a coefficient of thermal expansion that approximate that of the chips (e.g. silicon, silicon carbide, silicon germanium, germanium or SiCGe) to surround chips. After removal of the support wafer, processing of multi-chip module is finished with wiring on a shared surface of multi-chip module and chip surface.

摘要翻译： 通过使支撑晶片上的预接线芯片对准并沉积具有接近芯片（例如硅，碳化硅，硅锗，锗或SiCGe）的热膨胀系数的非导电导热和非导电材料来构造多芯片模块 ）围绕芯片。 拆卸支撑晶片后，多芯片模块的处理通过多芯片模块和芯片表面的共享表面上的布线完成。

公开(公告)号：US06444402B1

公开(公告)日：2002-09-03

申请号：US09532187

申请日：2000-03-21

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H-L. Ma

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H-L. Ma

IPC分类号： G03C500

CPC分类号： H01L21/31144 ,  G03F7/0035 ,  G03F7/40 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/76816

摘要： Features of two or more distinct sizes designed to optimize performance of an integrated circuit device are formed by transferring a pattern from a resist patterned with features of a single minimum feature size for which a resist exposure tool is optimized to a layer of preferably soluble material such as germanium oxide. Portions of this pattern are then enlarged using a block-out mask and the resulting pattern transferred to a further underlying layer preferably using an anisotropic reactive ion etch. The soluble material can then be removed leaving a robust mask with differing feature sizes for further processing. Preferably, Damascene conductive lines and vias are formed by providing an insulator as the further underlying material and filling the openings with metal or other conductive material.

摘要翻译： 设计用于优化集成电路器件性能的两个或多个不同尺寸的特征通过将图案从具有抗蚀剂曝光工具优化的单个最小特征尺寸的特征的抗蚀剂转移到优选可溶性材料层而形成， 作为氧化锗。 然后使用阻挡掩模将该图案的部分放大，并且将所得到的图案优选地使用各向异性反应离子蚀刻转移到另一下层。 然后可以去除可溶性材料，留下具有不同特征尺寸的坚固的掩模，用于进一步处理。 优选地，通过提供绝缘体作为其他下层材料并用金属或其它导电材料填充开口来形成镶嵌导电线和通孔。

公开(公告)号：US06344416B1

公开(公告)日：2002-02-05

申请号：US09523480

申请日：2000-03-10

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak

IPC分类号： H01L21311

CPC分类号： H01L22/20 ,  C23C16/04 ,  C23C16/513 ,  C23C16/52 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/76229 ,  H01L21/8234 ,  Y10S438/911

摘要： Methods and apparatuses are disclosed that can introduce deliberate semiconductor film variation during semiconductor manufacturing to compensate for radial processing differences, to determine optimal device characteristics, or produce small production runs. The present invention radially varies the thickness and/or composition of a semiconductor film to compensate for a known radial variation in the semiconductor film that is caused by performing a subsequent semiconductor processing step on the semiconductor film. Additionally, methods and apparatuses are disclosed that can introduce deliberate semiconductor film variations to determine optimal device characteristics or produce small production runs. Introducing semiconductor film variations, such as thickness variations and/or composition variations, allow different devices to be made. A number of devices may be made having variations in semiconductor film. Because the semiconductor film has variations between the devices, device characteristics of the devices should be different. By measuring the device characteristics of devices having the variations, the device with the optimum device characteristic may be chosen, thereby indicating the appropriate semiconductor film thickness and/or composition. Moreover, small production runs of the same devices, having different characteristics, will allow the end user to select the appropriate devices for their needs.

摘要翻译： 公开了可以在半导体制造期间引入有意的半导体膜变化以补偿径向处理差异，确定最佳器件特性或产生小的生产运行的方法和装置。 本发明径向地改变半导体膜的厚度和/或组成，以补偿半导体膜中已知的半导体膜的径向变化，这是通过在半导体膜上进行随后的半导体处理步骤引起的。另外，公开了可以 引入有意识的半导体薄膜变化以确定最佳的器件特性或产生小的生产运行。 引入半导体薄膜变化，例如厚度变化和/或组成变化，允许制造不同的装置。 可以制造多个器件，其具有半导体膜的变化。 因为半导体薄膜在器件之间有变化，所以器件的器件特性应该是不同的。 通过测量具有变化的器件的器件特性，可以选择具有最佳器件特性的器件，从而指示适当的半导体膜厚度和/或组成。 此外，相同设备的小生产运行具有不同的特性，将允许最终用户根据需要选择适当的设备。

公开(公告)号：US06333229B1

公开(公告)日：2001-12-25

申请号：US09523839

申请日：2000-03-13

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak

IPC分类号： H01L21336

CPC分类号： H01L29/66621 ,  H01L21/28044 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4925 ,  H01L29/7834

摘要： A viable T-gate FET is produced even when the cap of the “T” is mis-aligned from the stem of the “T”. A subtractive etch is used to selectively etch the material forming the cap of the T-gate and the material forming the stem of the T-gate in order to avoid the etching away of portions of the stem if the cap is mis-aligned relative to the stem. To that end, germanium (Ge) may be used as the material for the cap of the T-gate and poly silicon (polySi) may be used as the material for the stem of the T-gate. Since germanium can be etched selectively relative to silicon from 10:1 to as much as 20:1, the cap of the T can be formed without appreciable damage to the stem portion and thus without damage to the resultant FET device.

摘要翻译： 即使当“T”的盖与“T”的杆不对齐时，也会产生可行的T型栅极FET。 使用减法蚀刻来选择性地蚀刻形成T形栅的帽和形成T形栅的杆的材料的材料，以避免如果帽相对于 茎。 为此，可以使用锗（Ge）作为T型栅极的盖的材料，并且可以使用多晶硅（polySi）作为T型栅极的材料。 由于锗可以相对于硅选择性地从10:1蚀刻到多达20:1，所以可以形成T的帽，而不会对柄部产生明显的损害，从而不会损坏所得到的FET器件。

公开(公告)号：US06221680B1

公开(公告)日：2001-04-24

申请号：US09127132

申请日：1998-07-31

申请人： Mark C. Hakey ,  Steven J. Holmes ,  David Horak ,  Toshiharu Furukawa

发明人： Mark C. Hakey ,  Steven J. Holmes ,  David Horak ,  Toshiharu Furukawa

IPC分类号： H01L2100

CPC分类号： H01L21/0273 ,  G03F7/094 ,  H01L21/02129 ,  H01L21/02271 ,  H01L21/312 ,  H01L21/31625 ,  H01L27/10861

摘要： The present invention relates to a method for providing patterned recess formation in a previously recessed area of a semiconductor structure, i.e. DRAM trench capacitor, using acid diffusion to selectively activate some, but not all of the acid sensitive material that is filled within the recessed areas of such structures. By employing the method of the present invention, it is possible to recess all the previously recessed areas at the same time providing the same level of recessed acid sensitive material within the previous recessed areas, recess some of the previously recessed areas to a desired level leaving other portions of the structure unrecessed, or recessing the previously recessed areas to contain different levels of the acid sensitive material.

摘要翻译： 本发明涉及一种用于在半导体结构（即DRAM沟槽电容器）的预先凹入的区域中提供图案化的凹陷形成的方法，其使用酸扩散来选择性地激活填充在凹陷区域内的一些但不是全部的酸敏感材料 的这种结构。 通过采用本发明的方法，可以同时在所有先前的凹陷区域内提供相同水平的凹入的酸敏感材料，同时将所有先前凹陷的区域都凹进，将一些先前凹陷的区域凹入到期望的水平位置 结构的其他部分不能被加工，或者使先前凹陷的区域凹陷以包含不同水平的酸敏感材料。