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    Photosensitive semiconductor package with support member and method for fabricating the same
    62.
    发明申请
    Photosensitive semiconductor package with support member and method for fabricating the same 审中-公开
    具有支撑构件的感光半导体封装及其制造方法

    公开(公告)号：US20050184404A1

    公开(公告)日：2005-08-25

    申请号：US10835343

    申请日：2004-04-28

    申请人： Chih-Ming Huang ,  Cheng-Hsu Hsiao ,  Chien-Ping Huang

    发明人： Chih-Ming Huang ,  Cheng-Hsu Hsiao ,  Chien-Ping Huang

    IPC分类号： H01L21/48 ,  H01L23/04 ,  H01L23/28 ,  H01L31/0203

    CPC分类号： H01L27/14683 ,  H01L23/04 ,  H01L24/97 ,  H01L27/14618 ,  H01L31/0203 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00

    摘要： A photosensitive semiconductor package with a support member and its fabrication method are provided. The support member having a receiving space is placed on an upper surface of a substrate. An encapsulation body is formed on the substrate and bonded with an outer wall of the support member. At least one chip is mounted on a predetermined area of the substrate exposed via the receiving space, and is electrically connected to the substrate. A light-permeable lid is attached to the support member and the encapsulation body to seal the receiving space. A plurality of solder balls or contact lands are formed on a lower surface of the substrate. By provision of the support member, there is no need to use an insert mold, such that the substrate would not be damaged by the insert mold, and bond fingers on the substrate would not be contaminated by the insert mold.

    摘要翻译： 提供具有支撑构件的光敏半导体封装及其制造方法。 具有接收空间的支撑构件被放置在基板的上表面上。 封装体形成在基板上并与支撑构件的外壁结合。 至少一个芯片安装在经由接收空间暴露的衬底的预定区域上，并且电连接到衬底。 透光盖附接到支撑构件和封装体以密封接收空间。 在基板的下表面上形成多个焊球或接触焊盘。 通过设置支撑构件，不需要使用插入模具，使得基板不会被插入模具损坏，并且基板上的键合指不会被插入模具污染。

    Semiconductor package with heat sink
    64.
    发明授权
    Semiconductor package with heat sink 有权
    半导体封装带散热片

    公开(公告)号：US06856015B1

    公开(公告)日：2005-02-15

    申请号：US10719726

    申请日：2003-11-21

    申请人： Chien-Ping Huang ,  Cheng-Hsu Hsiao ,  Shih-Kuang Chiu

    发明人： Chien-Ping Huang ,  Cheng-Hsu Hsiao ,  Shih-Kuang Chiu

    IPC分类号： H01L21/48 ,  H01L23/367 ,  H01L23/12

    CPC分类号： H01L23/367 ,  H01L21/4882 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/72 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/16315 ,  H01L2924/00012 ,  H01L2924/00015

    摘要： A semiconductor package includes a substrate having a top surface and a bottom surface; at least one chip mounted on the top surface of the substrate and electrically connected to the substrate; a heat sink attached to the top surface of the substrate by an adhesive material applied therebetween; and a plurality of solder balls implanted on the bottom surface of the substrate. The heat sink has a flat portion and a support portion connected to the flat portion. The support portion has at least one recess portion facing toward the top surface of the substrate and at least one burr formed on an interior surface of the recess portion such that the adhesive material can fill the recess portion and submerge the burr to provide an anchoring effect to firmly secure the heat sink in position on the substrate.

    摘要翻译： 半导体封装包括具有顶表面和底表面的衬底; 至少一个芯片安装在所述基板的顶表面上并电连接到所述基板; 通过施加在其之间的粘合剂材料附接到基板的顶表面的散热器; 以及注入到所述基板的底面上的多个焊球。 散热器具有平坦部分和连接到平坦部分的支撑部分。 所述支撑部分具有至少一个面向所述基板的顶表面的凹部和至少一个形成在所述凹部的内表面上的毛刺，使得所述粘合剂材料可以填充所述凹陷部分并浸没所述毛刺以提供锚固效果 以将散热器牢固地固定在基板上的适当位置。

    Semiconductor package with stacked chips
    65.
    发明授权
    Semiconductor package with stacked chips 有权
    半导体封装堆叠芯片

    公开(公告)号：US06541870B1

    公开(公告)日：2003-04-01

    申请号：US09990788

    申请日：2001-11-14

    申请人： Chien-Ping Huang ,  Tzong-Da Ho ,  cheng-Hsu Hsiao

    发明人： Chien-Ping Huang ,  Tzong-Da Ho ,  cheng-Hsu Hsiao

    IPC分类号： H01L2348

    CPC分类号： H01L25/0657 ,  H01L23/3121 ,  H01L23/4334 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

    摘要： A semiconductor package with stacked chips is proposed, wherein at least two chips are stacked on a chip carrier in a stagger manner as to dispose a second chip on a first chip, and a supporting element is disposed on the second chip and dimensioned to cover area on the second chip with no support from the first chip. The supporting element provides support to the second chip, allowing bonding wires to be successfully connected to the second chip, without the occurrence of cracks of the second chip. The supporting element can be formed on its lower surface with protruding portions positioned outside edge sides of the second chip; this is to enhance structural strength of the supporting element, and help maintain the second chip intact in structure during wire bonding. The supporting element can further have its upper surface to be exposed to the atmosphere; this improves heat dissipating efficiency of the semiconductor package.

    摘要翻译： 提出了一种具有堆叠芯片的半导体封装，其中至少两个芯片以错开的方式堆叠在芯片载体上，以将第二芯片布置在第一芯片上，并且支撑元件设置在第二芯片上并且尺寸设置为覆盖区域 在第二个芯片上没有第一个芯片的支持。 支撑元件为第二芯片提供支撑，允许接合线成功地连接到第二芯片，而不会发生第二芯片的裂纹。 支撑元件可以在其下表面上形成有位于第二芯片的边缘侧的突出部分; 这是为了增强支撑元件的结构强度，并且有助于在引线接合期间保持第二芯片的结构完整。 支撑元件还可以使其上表面暴露于大气中; 这提高了半导体封装的散热效率。

    FABRICATION METHOD OF MULTI-CHIP STACK STRUCTURE
    66.
    发明申请
    FABRICATION METHOD OF MULTI-CHIP STACK STRUCTURE 有权
    多芯片堆叠结构的制作方法

    公开(公告)号：US20100255635A1

    公开(公告)日：2010-10-07

    申请号：US12818701

    申请日：2010-06-18

    申请人： Jung-Pin Huang ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chung-Lun Liu ,  Cheng-Hsu Hsiao

    发明人： Jung-Pin Huang ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chung-Lun Liu ,  Cheng-Hsu Hsiao

    IPC分类号： H01L21/60

    CPC分类号： H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48496 ,  H01L2224/49175 ,  H01L2224/78 ,  H01L2224/85001 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00

    摘要： A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.

    摘要翻译： 提出了一种多芯片堆叠结构及其制造方法，包括提供具有芯片基底和多个引线的引线框架，并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上，第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺，以通过多个第一接合线将第一芯片电连接到引线，以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中，通过凸块将引线框倒置放置到加热块， 以及执行第二引线接合处理，以通过多个第二接合线将所述第二芯片电连接到所述引线。 凸块用于将引线支撑到一定高度，以便使接合线不会接触加热块，并且在现有技术的第二引线接合过程中不需要使用第二加热块，从而节省了时间和成本 在制造过程中。 此外，由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应，可以防止电性能和电不匹配受到不利影响的常规问题。

    Multi-chip stack structure and fabrication method thereof
    67.
    发明授权
    Multi-chip stack structure and fabrication method thereof 有权
    多芯片堆叠结构及其制造方法

    公开(公告)号：US07768106B2

    公开(公告)日：2010-08-03

    申请号：US12077003

    申请日：2008-03-13

    申请人： Jung-Ping Huang ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chung-Lun Liu ,  Cheng-Hsu Hsiao

    发明人： Jung-Ping Huang ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chung-Lun Liu ,  Cheng-Hsu Hsiao

    IPC分类号： H01L23/495 ,  H01L21/00

    CPC分类号： H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48496 ,  H01L2224/49175 ,  H01L2224/78 ,  H01L2224/85001 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00

    摘要： A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.

    摘要翻译： 提出了一种多芯片堆叠结构及其制造方法，包括提供具有芯片基底和多个引线的引线框架，并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上，第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺，以通过多个第一接合线将第一芯片电连接到引线，以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中，通过凸块将引线框倒置放置到加热块， 以及执行第二引线接合处理，以通过多个第二接合线将所述第二芯片电连接到所述引线。 凸块用于将引线支撑到一定高度，以便使接合线不会接触加热块，并且在现有技术的第二引线接合过程中不需要使用第二加热块，从而节省了时间和成本 在制造过程中。 此外，由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应，可以防止电性能和电不匹配受到不利影响的常规问题。