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公开(公告)号：US07768106B2
公开(公告)日：2010-08-03
申请号：US12077003
申请日：2008-03-13
IPC分类号： H01L23/495 , H01L21/00
CPC分类号： H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L24/85 , H01L25/50 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48496 , H01L2224/49175 , H01L2224/78 , H01L2224/85001 , H01L2924/00014 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/00
摘要： A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.
摘要翻译： 提出了一种多芯片堆叠结构及其制造方法，包括提供具有芯片基底和多个引线的引线框架，并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上，第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺，以通过多个第一接合线将第一芯片电连接到引线，以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中，通过凸块将引线框倒置放置到加热块， 以及执行第二引线接合处理，以通过多个第二接合线将所述第二芯片电连接到所述引线。 凸块用于将引线支撑到一定高度，以便使接合线不会接触加热块，并且在现有技术的第二引线接合过程中不需要使用第二加热块，从而节省了时间和成本 在制造过程中。 此外，由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应，可以防止电性能和电不匹配受到不利影响的常规问题。
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公开(公告)号：US07981729B2
公开(公告)日：2011-07-19
申请号：US12818701
申请日：2010-06-18
IPC分类号： H01L21/60
CPC分类号： H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L24/85 , H01L25/50 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48496 , H01L2224/49175 , H01L2224/78 , H01L2224/85001 , H01L2924/00014 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/00
摘要： A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.
摘要翻译： 提出了一种多芯片堆叠结构及其制造方法，包括提供具有芯片基底和多个引线的引线框架，并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上，第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺，以通过多个第一接合线将第一芯片电连接到引线，以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中，通过凸块将引线框倒置放置到加热块， 以及执行第二引线接合处理，以通过多个第二接合线将所述第二芯片电连接到所述引线。 凸块用于将引线支撑到一定高度，以便使接合线不会接触加热块，并且在现有技术的第二引线接合过程中不需要使用第二加热块，从而节省了时间和成本 在制造过程中。 此外，由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应，可以防止电性能和电不匹配受到不利影响的常规问题。
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公开(公告)号：US20100255635A1
公开(公告)日：2010-10-07
申请号：US12818701
申请日：2010-06-18
IPC分类号： H01L21/60
CPC分类号： H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L24/85 , H01L25/50 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48496 , H01L2224/49175 , H01L2224/78 , H01L2224/85001 , H01L2924/00014 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/00
摘要： A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.
摘要翻译： 提出了一种多芯片堆叠结构及其制造方法，包括提供具有芯片基底和多个引线的引线框架，并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上，第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺，以通过多个第一接合线将第一芯片电连接到引线，以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中，通过凸块将引线框倒置放置到加热块， 以及执行第二引线接合处理，以通过多个第二接合线将所述第二芯片电连接到所述引线。 凸块用于将引线支撑到一定高度，以便使接合线不会接触加热块，并且在现有技术的第二引线接合过程中不需要使用第二加热块，从而节省了时间和成本 在制造过程中。 此外，由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应，可以防止电性能和电不匹配受到不利影响的常规问题。
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公开(公告)号：US20080224289A1
公开(公告)日：2008-09-18
申请号：US12077003
申请日：2008-03-13
IPC分类号： H01L23/495 , H01L21/00
CPC分类号： H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L24/85 , H01L25/50 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48496 , H01L2224/49175 , H01L2224/78 , H01L2224/85001 , H01L2924/00014 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/00
摘要： A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.
摘要翻译： 提出了一种多芯片堆叠结构及其制造方法，包括提供具有芯片基底和多个引线的引线框架，并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上，第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺，以通过多个第一接合线将第一芯片电连接到引线，以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中，通过凸块将引线框倒置放置到加热块， 以及执行第二引线接合处理，以通过多个第二接合线将所述第二芯片电连接到所述引线。 凸块用于将引线支撑到一定高度，以便使接合线不会接触加热块，并且在现有技术的第二引线接合过程中不需要使用第二加热块，从而节省了时间和成本 在制造过程中。 此外，由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应，可以防止电性能和电不匹配受到不利影响的常规问题。
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公开(公告)号：US20090014860A1
公开(公告)日：2009-01-15
申请号：US12011832
申请日：2008-01-29
CPC分类号： H01L25/0652 , H01L25/18 , H01L2224/32145 , H01L2224/48227 , H01L2224/73215 , H01L2224/73265 , H01L2224/92247 , H01L2225/06562 , H01L2924/00012
摘要： A multi-chip stack structure and a manufacturing method thereof are provided. The fabrication method includes the steps of: providing a chip carrier having a first surface and a second surface opposing thereto and at least a first chip and a second chip mounted on the first surface; electrically connecting the chips to the chip carrier by a plurality of bonding wires; and stacking at least a third chip on the first and second chips by a film deposed therebetween, wherein the third chip is stepwise stacked on the first chip and at least a part of the bonding wire connected to the second chip is covered by the film, and electrically connecting the third chip and the chip carrier by a bonding wire, thereby enabling a plurality of chips to be stacked on the chip carrier to enhance the electrical performance of electronic products.
摘要翻译： 提供了一种多芯片堆叠结构及其制造方法。 该制造方法包括以下步骤：提供具有与其相对的第一表面和第二表面的芯片载体和至少安装在第一表面上的第一芯片和第二芯片; 通过多个接合线将芯片电连接到芯片载体上; 并且通过其间放置的膜将第一和第二芯片上的至少第三芯片堆叠起来，其中第三芯片逐步堆叠在第一芯片上，并且连接到第二芯片的键合线的至少一部分被膜覆盖， 并通过接合线电连接第三芯片和芯片载体，从而能够将多个芯片堆叠在芯片载体上，以增强电子产品的电气性能。
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6.发明申请Multi-chip semiconductor device having leads and method for fabricating the same 审中-公开具有引线的多芯片半导体器件及其制造方法公开(公告)号：US20080283982A1
公开(公告)日：2008-11-20
申请号：US12152802
申请日：2008-05-15
IPC分类号： H01L21/58 , H01L23/495
CPC分类号： H05K1/141 , H01L23/3121 , H01L23/49811 , H01L23/49816 , H01L23/49861 , H01L24/48 , H01L24/81 , H01L24/85 , H01L24/97 , H01L25/0655 , H01L2224/48091 , H01L2224/48247 , H01L2224/81801 , H01L2224/85 , H01L2224/97 , H01L2924/00014 , H01L2924/01033 , H01L2924/01082 , H01L2924/15311 , H01L2924/181 , H05K3/3421 , H05K3/3436 , H05K2201/1034 , H05K2201/10659 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention proposes a multi-chip semiconductor device having leads and a method for fabricating the same. The method includes the steps of: providing a substrate having a plurality of connection pads disposed on a surface thereof; mounting a plurality of semiconductor chips on the surface of the substrate, and electrically connecting the semiconductor chips to the surface of the substrate; forming an encapsulant on the substrate to encapsulate the semiconductor chips and expose the connection pads to form a package unit; and providing a lead frame having a plurality of leads, and electrically connecting the connection pads exposed from the package unit to the leads of the lead frame to form a multi-chip semiconductor device having leads, thereby forming a multi-chip semiconductor device having leads. By the multi-chip semiconductor device and the method for fabricating the same as proposed in the present invention, problems like poor reliability caused by stress induced by several types of materials in a semiconductor package into which a substrate and leads are integrated, moisture absorption by an encapsulated substrate, and cracks developed as a result of moisture absorption by the substrate can be avoided.
摘要翻译： 本发明提出一种具有引线的多芯片半导体器件及其制造方法。 该方法包括以下步骤：提供具有设置在其表面上的多个连接焊盘的基板; 将多个半导体芯片安装在所述基板的表面上，并且将所述半导体芯片电连接到所述基板的表面; 在衬底上形成密封剂以封装半导体芯片并暴露连接焊盘以形成封装单元; 并且提供具有多个引线的引线框架，并且将从封装单元暴露的连接焊盘电连接到引线框架的引线以形成具有引线的多芯片半导体器件，从而形成具有引线的多芯片半导体器件 。 通过本发明中提出的多芯片半导体器件及其制造方法，由半导体封装中由几种材料引起的应力引起的可靠性差的问题，其中衬底和引线被集成到其中，由于 可以避免被封装的基材和由于基材吸湿而显影的裂纹。
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公开(公告)号：US20070108571A1
公开(公告)日：2007-05-17
申请号：US11649144
申请日：2007-01-02
申请人： Jung-Pin Huang , Chin-Huang Chang , Chung-Lun Liu
发明人： Jung-Pin Huang , Chin-Huang Chang , Chung-Lun Liu
IPC分类号： H01L23/495 , H01L21/00
CPC分类号： H01L23/49575 , H01L23/3135 , H01L23/49531 , H01L24/48 , H01L24/49 , H01L2224/32145 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/48247 , H01L2224/4911 , H01L2924/00014 , H01L2924/14 , H01L2924/1532 , H01L2924/181 , H01L2924/19107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package with stacked chips and a method for fabricating the same are proposed. The semiconductor package includes a lead frame having a plurality of leads and supporting extensions; at least one preformed package having an active surface, and a non-active surface attached to the supporting extensions of the lead frame; at least one chip mounted on the active surface of the preformed package; a plurality of bonding wires for electrically interconnecting the lead frame, the preformed package and the chip; and an encapsulant for encapsulating the preformed package, the chip, the bonding wire and a portion of the lead frame. The active surface of the preformed package serves for carrying the chip and can be used as a wire jumper, so as to solve a known good die (KGD) problem of a multi-chip module.
摘要翻译： 提出了一种具有堆叠芯片的半导体封装及其制造方法。 半导体封装包括具有多个引线和支撑延伸部的引线框架; 至少一个具有活性表面的预制包装和连接到引线框架的支撑延伸部的非活性表面; 至少一个芯片安装在所述预制包装的有效表面上; 用于将引线框架，预成型封装和芯片电连接的多个接合线; 以及用于封装预制包装，芯片，接合线和引线框架的一部分的密封剂。 预制包装的活性表面用于承载芯片，并且可以用作跳线，以便解决多芯片模块的已知的良好的裸片（KGD）问题。
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公开(公告)号：US20090140440A1
公开(公告)日：2009-06-04
申请号：US12266830
申请日：2008-11-07
申请人： Chung-Lun Liu , Jung-Pin Huang , Yi-Feng Chang , Chin-Huang Chang
发明人： Chung-Lun Liu , Jung-Pin Huang , Yi-Feng Chang , Chin-Huang Chang
CPC分类号： H01L25/50 , H01L21/56 , H01L23/3107 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L25/0657 , H01L25/18 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83 , H01L2224/858 , H01L2224/8592 , H01L2225/06506 , H01L2225/0651 , H01L2225/06555 , H01L2225/06562 , H01L2225/06575 , H01L2924/00014 , H01L2924/01033 , H01L2924/01082 , H01L2924/1436 , H01L2924/1438 , H01L2924/15311 , H01L2924/15313 , H01L2924/15321 , H01L2924/15323 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： A multi-chip stack structure and a method for fabricating the same are provided. The method for fabricating a multi-chip stack structure includes disposing a first chip group comprising a plurality of first chips on a chip carrier by using a step-like manner, disposing a second chip on the first chip on top of the first chip group, electrically connecting the first chip group and the second chip to the chip carrier through bonding wires, using film over wire (FOW) to stack a third chip on the first and the second chips with an insulative film provided therebetween, wherein the insulative film covers part of the ends of the bonding wires of the first chip on the top of the first group and at least part of the second chip, and electrically connecting the third chip to the chip carrier through bonding wires, thereby preventing directly disposing on a first chip a second chip having a planar size far smaller than that of the first chip as in the prior art that increases height of the entire structure and increases the wiring bonding difficulty.
摘要翻译： 提供了一种多芯片堆叠结构及其制造方法。 制造多芯片堆叠结构的方法包括通过使用阶梯状方式将包括多个第一芯片的第一芯片组布置在芯片载体上，将第二芯片设置在第一芯片组的顶部上的第一芯片上， 通过接合线将第一芯片组和第二芯片电连接到芯片载体上，使用薄膜覆盖线（FOW）来在第一芯片和第二芯片之间设置绝缘膜，其中绝缘膜覆盖部分 在第一组的顶部和第二芯片的至少一部分上的第一芯片的接合线的端部，并且通过接合线将第三芯片电连接到芯片载体，从而防止直接布置在第一芯片上 第二芯片的平面尺寸远远小于现有技术中的第一芯片的平面尺寸，这增加了整个结构的高度并增加了布线粘合难度。
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公开(公告)号：US07266888B2
公开(公告)日：2007-09-11
申请号：US11043496
申请日：2005-01-25
申请人： Chin-Huang Chang , Chin-Tien Chiu , Chung-Lun Liu
发明人： Chin-Huang Chang , Chin-Tien Chiu , Chung-Lun Liu
CPC分类号： H01L23/49822 , H01L23/49838 , H01L24/45 , H01L24/48 , H01L2224/45144 , H01L2224/48227 , H01L2224/48228 , H01L2924/00014 , H01L2924/01079 , H01L2924/15311 , H01L2924/181 , H01L2924/3025 , H01L2924/3511 , H05K1/0271 , H05K3/28 , H05K2201/09663 , H05K2201/09781 , Y10T29/49117 , Y10T29/49124 , Y10T29/49128 , Y10T29/49155 , Y10T29/4916 , H01L2224/05599 , H01L2924/00012
摘要： A and method for fabricating a warpage-preventive circuit board is provided, wherein a plurality of conductive traces are formed on a surface of an electrically-insulative core layer, and a plurality of discontinuous dummy circuit regions are disposed on the surface of the electrically-insulative core layer at area free of the conductive traces, with adjacent dummy circuit regions being spaced apart by at least a chink. During a high-temperature fabrication process, the dummy circuit regions help reduce thermal stress and the chinks absorb thermal expansion of the dummy circuit regions, to thereby prevent warpage of the circuit board and cracks of a chip mounted on the circuit board, such that yield and reliability of fabricated semiconductor devices can be improved.
摘要翻译： 提供了一种制造防翘曲电路板的方法，其中在电绝缘芯层的表面上形成多个导电迹线，并且多个不连续的虚设电路区域设置在电绝缘性电路板的表面上， 绝缘芯层在没有导电迹线的区域处，其中相邻的虚拟电路区域至少间隔开。 在高温制造过程中，虚拟电路区域有助于降低热应力，并且汲取吸收虚拟电路区域的热膨胀，从而防止电路板翘曲和安装在电路板上的芯片的裂纹，使得屈服 并且可以提高制造的半导体器件的可靠性。
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公开(公告)号：US08896130B2
公开(公告)日：2014-11-25
申请号：US12266830
申请日：2008-11-07
申请人： Chung-Lun Liu , Jung-Pin Huang , Yi-Feng Chang , Chin-Huang Chang
发明人： Chung-Lun Liu , Jung-Pin Huang , Yi-Feng Chang , Chin-Huang Chang
CPC分类号： H01L25/50 , H01L21/56 , H01L23/3107 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L25/0657 , H01L25/18 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83 , H01L2224/858 , H01L2224/8592 , H01L2225/06506 , H01L2225/0651 , H01L2225/06555 , H01L2225/06562 , H01L2225/06575 , H01L2924/00014 , H01L2924/01033 , H01L2924/01082 , H01L2924/1436 , H01L2924/1438 , H01L2924/15311 , H01L2924/15313 , H01L2924/15321 , H01L2924/15323 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： A multi-chip stack structure and a method for fabricating the same are provided. The method for fabricating a multi-chip stack structure includes disposing a first chip group comprising a plurality of first chips on a chip carrier by using a step-like manner, disposing a second chip on the first chip on top of the first chip group, electrically connecting the first chip group and the second chip to the chip carrier through bonding wires, using film over wire (FOW) to stack a third chip on the first and the second chips with an insulative film provided therebetween, wherein the insulative film covers part of the ends of the bonding wires of the first chip on the top of the first group and at least part of the second chip, and electrically connecting the third chip to the chip carrier through bonding wires, thereby preventing directly disposing on a first chip a second chip having a planar size far smaller than that of the first chip as in the prior art that increases height of the entire structure and increases the wiring bonding difficulty.
摘要翻译： 提供了一种多芯片堆叠结构及其制造方法。 制造多芯片堆叠结构的方法包括通过使用阶梯状方式将包括多个第一芯片的第一芯片组布置在芯片载体上，将第二芯片设置在第一芯片组的顶部上的第一芯片上， 通过接合线将第一芯片组和第二芯片电连接到芯片载体上，使用薄膜覆盖线（FOW）来在第一芯片和第二芯片之间设置绝缘膜，其中绝缘膜覆盖部分 在第一组的顶部和第二芯片的至少一部分上的第一芯片的接合线的端部，并且通过接合线将第三芯片电连接到芯片载体，从而防止直接布置在第一芯片上 第二芯片的平面尺寸远远小于现有技术中的第一芯片的平面尺寸，这增加了整个结构的高度并增加了布线粘合难度。
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