公开(公告)号：US5319228A

公开(公告)日：1994-06-07

申请号：US617199

申请日：1990-11-23

申请人： Tohru Ozaki

发明人： Tohru Ozaki

IPC分类号： H01L21/76 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L29/94 ,  H01L29/68 ,  H01L29/78 ,  H01L29/92

CPC分类号： H01L29/945 ,  H01L27/10829 ,  Y10S257/908 ,  Y10S257/909 ,  Y10S257/91 ,  Y10S257/911

摘要： A semiconductor memory device having a trench-type capacitor configuration is provided. The device comprises an element isolation insulating film formed on the surface of the substrate in the vicinity of the trenches. The insulating film includes a thickness-reducing region to which the inclined end portion of the capacitor electrode is connected.

摘要翻译： 提供具有沟槽型电容器配置的半导体存储器件。 该器件包括在沟槽附近形成在衬底表面上的元件隔离绝缘膜。 绝缘膜包括连接电容器电极的倾斜端部的厚度减小区域。

公开(公告)号：US5218018A

公开(公告)日：1993-06-08

申请号：US635970

申请日：1990-12-31

申请人： Akira Tominaga ,  Reiziro Nishida ,  Hiroshi Inoue ,  Motoshi Yabuta ,  Yoshio Sasaki ,  Akira Kasari ,  Hiroshi Igarashi ,  Tohru Ozaki

发明人： Akira Tominaga ,  Reiziro Nishida ,  Hiroshi Inoue ,  Motoshi Yabuta ,  Yoshio Sasaki ,  Akira Kasari ,  Hiroshi Igarashi ,  Tohru Ozaki

IPC分类号： B05D7/00 ,  C08G59/20 ,  C08G59/68 ,  C09D5/38 ,  C09D163/00 ,  C09D201/06

CPC分类号： B05D7/532 ,  C08G59/20 ,  C08G59/68 ,  C09D163/00 ,  C09D201/06 ,  C09D5/38

摘要： A thermosetting coating composition comprising as essential components:(a) a hydroxyl group-containing base resin,(b) an alicyclic polyepoxide crosslinking agent, and(c) a catalyst selected from the group consisting of a quaternary ammonium hydroxide and a metal chelate.

摘要翻译： 一种热固性涂料组合物，其包含作为必要组分的（a）含羟基的基础树脂，（b）脂环族聚环氧化物交联剂和（c）选自季铵氢氧化物和金属螯合物的催化剂。

公开(公告)号：US07812384B2

公开(公告)日：2010-10-12

申请号：US12109817

申请日：2008-04-25

申请人： Tohru Ozaki

发明人： Tohru Ozaki

IPC分类号： H01G7/06

CPC分类号： H01L28/60 ,  G11C11/22 ,  H01L27/105 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55

摘要： According to an aspect of the present invention, there is provided a semiconductor device including: a transistor including: a source, a drain and a gate; first and second plugs on the source and the drain; a third plug on the gate to have a top face higher than that of the first plug; an interlayer insulating film covering the transistor and the first to the third plugs; a ferroelectric capacitor on the interlayer insulating film, one electrode thereof being connected to the first plug; a barrier film covering surfaces of the ferroelectric capacitor and the interlayer insulating film to prevent a substance affecting the ferroelectric capacitor from entering therethrough; and fourth and fifth plugs disposed on the second and the third plugs and connected thereto through connection holes formed in the barrier film.

摘要翻译： 根据本发明的一个方面，提供了一种半导体器件，包括：晶体管，包括：源极，漏极和栅极; 源极和漏极上的第一和第二插头; 栅极上的第三个插头具有高于第一插头的顶面; 覆盖晶体管和第一至第三插头的层间绝缘膜; 层间绝缘膜上的铁电电容器，其一个电极连接到第一插头; 覆盖铁电电容器和层间绝缘膜的表面的阻挡膜，以防止影响铁电电容器的物质进入其中; 以及设置在第二和第三插头上的第四和第五插头，并且通过形成在阻挡膜中的连接孔与其连接。

公开(公告)号：US07091537B2

公开(公告)日：2006-08-15

申请号：US10933382

申请日：2004-09-03

申请人： Tohru Ozaki

发明人： Tohru Ozaki

IPC分类号： H01L29/76

CPC分类号： H01L27/1159 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/11502 ,  H01L27/11585

摘要： A ferroelectric memory device includes a first trench formed in a semiconductor substrate and having a first depth, a second trench formed in the substrate and having a second depth, a first element isolation insulating film buried in the first trench, a first gate electrode formed in a lower region of the second trench, a first insulating film formed in an upper region of the second trench, first and second diffusion layers formed in the substrate on both side surface in the second trench, a first ferroelectric capacitor disposed on the first diffusion layer, a first contact disposed on the first ferroelectric capacitor, a first wiring layer disposed on the first contact, a second contact disposed on the second diffusion layer, and a second wiring layer disposed on the second contact and disposed in the same level as that of the first wiring layer.

摘要翻译： 铁电存储器件包括形成在半导体衬底中并具有第一深度的第一沟槽，形成在衬底中并具有第二深度的第二沟槽，埋在第一沟槽中的第一元件隔离绝缘膜，形成在第一沟槽中的第一栅电极 第二沟槽的下部区域，形成在第二沟槽的上部区域中的第一绝缘膜，在第二沟槽的两侧面上形成在基板中的第一和第二扩散层，设置在第一扩散层上的第一铁电电容器 设置在第一铁电电容器上的第一触点，设置在第一触点上的第一布线层，设置在第二扩散层上的第二触点和设置在第二触点上的第二布线层， 第一布线层。

公开(公告)号：US06635933B2

公开(公告)日：2003-10-21

申请号：US09953306

申请日：2001-09-17

申请人： Yutaka Ishibashi ,  Yusuke Kohyama ,  Tohru Ozaki

发明人： Yutaka Ishibashi ,  Yusuke Kohyama ,  Tohru Ozaki

IPC分类号： H01L2976

CPC分类号： H01L27/10885 ,  H01L27/10852 ,  H01L27/10873 ,  H01L28/91

摘要： Capacitors are formed in the trenches made in an interlayer insulator made of silicon oxide. An insulating film (e.g., a silicon nitride film) is provided on the sides of each trench of the interlayer insulator. A storage electrode made of ruthenium or the like is provided in each trench of the interlayer insulator. A capacitor insulating film made of BSTO or the like is formed on the storage electrode. A plate electrode made of ruthenium or the like is formed on the capacitor insulating film. The plate electrode is common to all capacitors provided. Any two adjacent capacitors are electrically isolated by the interlayer insulator and the insulating film provided on the sides of the trenches of the interlayer insulator.

公开(公告)号：US06521929B2

公开(公告)日：2003-02-18

申请号：US09816245

申请日：2001-03-26

申请人： Tohru Ozaki

发明人： Tohru Ozaki

IPC分类号： H01L27108

CPC分类号： H01L27/11502 ,  H01L21/76838 ,  H01L28/55

摘要： A semiconductor device having ferroelectric memory cells has memory cell transistors each including first and second source/drain regions. Plug electrodes are formed in contact with the first and second source/drain regions, respectively. A ferroelectric capacitor is formed on the plug electrode connected to the first source/drain region. The ferroelectric capacitor includes a first lower electrode formed on the plug electrode, a ferroelectric film formed on the first lower electrode, and an upper electrode formed on the ferroelectric film. A second lower electrode is formed on the plug electrode connected to the second source/drain region. Wiring is formed to connect the upper electrode to the corresponding second lower electrode.

公开(公告)号：US06180973B2

公开(公告)日：2001-01-30

申请号：US09069853

申请日：1998-04-30

申请人： Tohru Ozaki

发明人： Tohru Ozaki

IPC分类号： H01L27108

CPC分类号： H01L27/10867 ,  H01L27/10832 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10873 ,  H01L27/10891

摘要： A semiconductor memory device includes a semiconductor substrate, an element isolation film formed on the substrate, element formation regions each defined in an island form in the surface of the substrate by the element isolation film, trenches formed in the element formation regions, respectively, capacitors each formed in a corresponding one of the trenches, each having a plate electrode formed of the substrate, a capacitor insulating film formed on the inner wall of the trench and a storage electrode filled in the trench with the capacitor insulating film disposed therebetween, transistors each formed in the element formation regions, and having a gate electrode which is formed to extend over the substrate and pass over the trench and the element formation region, a first impurity diffusion layer formed on one side of the gate electrode, a second impurity diffusion layer formed on the other side of the gate electrode, and channel regions formed on the element formation region on both sides of the trench below the gate electrode and respectively connected to the first and second impurity diffusion layers, connection electrodes for respectively connecting the storage electrodes to the first impurity diffusion layers, and signal transmission lines respectively connected to the second impurity diffusion layers.

摘要翻译： 半导体存储器件包括半导体衬底，形成在衬底上的元件隔离膜，通过元件隔离膜在衬底的表面中以岛状形成的元件形成区域，分别形成在元件形成区域中的沟槽，电容器 每个形成在对应的一个沟槽中，每个沟槽具有由衬底形成的平板电极，形成在沟槽的内壁上的电容器绝缘膜和填充在沟槽中的存储电极，其间设置有电容器绝缘膜，晶体管各自 形成在所述元件形成区域中，并且具有形成为在所述基板上延伸并越过所述沟槽和所述元件形成区域的栅电极，形成在所述栅电极的一侧上的第一杂质扩散层，第二杂质扩散层 形成在栅电极的另一侧上，以及形成在元件形成区上的沟道区 并且分别连接到第一和第二杂质扩散层，用于将存储电极分别连接到第一杂质扩散层的连接电极和分别连接到第二杂质扩散层的信号传输线。

公开(公告)号：US6162720A

公开(公告)日：2000-12-19

申请号：US217947

申请日：1998-12-22

申请人： Tohru Ozaki

发明人： Tohru Ozaki

IPC分类号： H01L27/04 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/44

CPC分类号： H01L27/10852 ,  H01L21/76831 ,  H01L21/76897 ,  H01L27/10861

摘要： A method of manufacturing a semiconductor device. First, a plurality of wires are arranged in parallel to one another, on a semiconductor substrate. Then, insulating films of a first group are formed on tops of the wires, respectively. Next, second insulating films of a second group are formed on sides of the wires, respectively. Further, among the wires there are formed insulating films of a third group which have upper surfaces located at a level not higher than upper surfaces of the insulating films of the second group. Thereafter, contact holes are formed by subjecting the insulating films of the third group to selectively etching. Finally, the contact holes are filled with electrically conductive material.

摘要翻译： 一种制造半导体器件的方法。 首先，在半导体基板上并列配置多条电线。 然后，分别在导线的顶部形成第一组的绝缘膜。 接下来，第二组的第二绝缘膜分别形成在导线的侧面上。 此外，在导线之间形成具有位于不高于第二组的绝缘膜的上表面的上表面的第三组的绝缘膜。 此后，通过对第三组的绝缘膜进行选择性蚀刻来形成接触孔。 最后，接触孔填充有导电材料。

公开(公告)号：US6078073A

公开(公告)日：2000-06-20

申请号：US878208

申请日：1997-06-18

申请人： Mariko Habu ,  Kazumasa Sunouchi ,  Masami Aoki ,  Tohru Ozaki

发明人： Mariko Habu ,  Kazumasa Sunouchi ,  Masami Aoki ,  Tohru Ozaki

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L27/10844 ,  H01L21/76897 ,  H01L27/10873

摘要： A gate electrode having a first insulating film laminated in the upper portion thereof is formed on a gate insulating film formed on a semiconductor substrate. A side wall is formed on the side wall of the gate electrode, and an insulating film is formed to cover the gate electrode and the side wall. Ion implantation is performed through the insulating film so that a diffusion layer is formed on the semiconductor substrate. An interlayer dielectric film is formed, and then the interlayer dielectric film and the insulating film are selectively etched so that an opening portion for exposing the gate insulating film is formed in a self-align manner with the gate electrode. Then, the gate insulating film in the bottom portion of the opening portion is removed so that the surface of the semiconductor substrate is exposed. Then, a wiring layer connected to the exposed surface of the semiconductor substrate is formed.

摘要翻译： 在形成在半导体衬底上的栅绝缘膜上形成具有层叠在其上部的第一绝缘膜的栅电极。 在栅电极的侧壁上形成侧壁，并且形成绝缘膜以覆盖栅电极和侧壁。 通过绝缘膜进行离子注入，从而在半导体衬底上形成扩散层。 形成层间电介质膜，然后选择性地蚀刻层间电介质膜和绝缘膜，从而以与栅电极自对准的方式形成露出栅极绝缘膜的开口部。 然后，去除开口部的底部的栅极绝缘膜，使得露出半导体基板的表面。 然后，形成与半导体基板的露出面连接的布线层。

公开(公告)号：US5838038A

公开(公告)日：1998-11-17

申请号：US478620

申请日：1995-06-07

申请人： Daisaburo Takashima ,  Shigeyoshi Watanabe ,  Tohru Ozaki ,  Takeshi Hamamoto ,  Yukihito Oowaki

发明人： Daisaburo Takashima ,  Shigeyoshi Watanabe ,  Tohru Ozaki ,  Takeshi Hamamoto ,  Yukihito Oowaki

IPC分类号： G11C7/18 ,  H01L27/108

CPC分类号： G11C7/18 ,  G11C2211/4013

摘要： A semiconductor memory device includes active regions arranged on a semiconductor substrate such that those of the active regions which are adjacent in the word line direction deviate in the bit line direction, MOS transistors respectively formed in the active regions and each having a source and a drain one of which is connected to the bit line, a plurality of trenches each arranged to another set of source an drain regions and arranged to deviate in the word line direction in the respective active regions, those of the trenches which are adjacent with a through word line disposed therebetween being arranged to deviate in the bit line direction so as to be set closer to each other, a plurality of storage electrodes respectively formed in the trenches with capacitor insulative films disposed therebetween, and connection electrodes arranged between the word lines and each connecting the other of the source and drain to the storage electrode.

摘要翻译： 半导体存储器件包括布置在半导体衬底上的有源区域，使得在字线方向上相邻的有源区域在位线方向偏离的有源区域分别形成在有源区域中并且各自具有源极和漏极 其中一个连接到位线，多个沟槽，每个沟槽被布置成另一组源极漏极区域，并且被布置成在相应的有源区域中的字线方向偏离，与通过字相邻的沟槽的那些沟槽 配置在它们之间的线被布置为在位线方向上偏离以使得彼此更靠近，分别形成在沟槽中的多个存储电极，其中设置有电容器绝缘膜，以及布置在字线和每个连接之间的连接电极 另一个源极和漏极到存储电极。