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    Low k interlevel dielectric layer fabrication methods
    61.
    发明授权
    Low k interlevel dielectric layer fabrication methods 有权

    公开(公告)号：US07521354B2

    公开(公告)日：2009-04-21

    申请号：US11266914

    申请日：2005-11-04

    申请人： Weimin Li ,  Zhiping Yin ,  William Budge

    发明人： Weimin Li ,  Zhiping Yin ,  William Budge

    IPC分类号： H01L21/31

    CPC分类号： H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/31633 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828

    摘要： A low k interlevel dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. An oxide comprising interlevel dielectric layer comprising carbon and having a dielectric constant no greater than 3.5 is formed over the substrate. After forming the carbon comprising dielectric layer, it is exposed to a plasma comprising oxygen effective to reduce the dielectric constant to below what it was prior to said exposing. A low k interlevel dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. In a chamber, an interlevel dielectric layer comprising carbon and having a dielectric constant no greater than 3.5 is plasma enhanced chemical vapor deposited over the substrate at subatmospheric pressure. After forming the carbon comprising dielectric layer, it is exposed to a plasma comprising oxygen at a subatmospheric pressure effective to reduce the dielectric constant by at least 10% below what it was prior to said exposing. The exposing occurs without removing the substrate from the chamber between the depositing and the exposing, and pressure within the chamber is maintained at subatmospheric between the depositing and the exposing.

    PREVENTION OF PHOTORESIST SCUMMING
    62.
    发明申请
    PREVENTION OF PHOTORESIST SCUMMING 有权
    防止光电子扫描

    公开(公告)号：US20080008942A1

    公开(公告)日：2008-01-10

    申请号：US11856556

    申请日：2007-09-17

    申请人： Zhiping Yin ,  Jingyi Bai

    发明人： Zhiping Yin ,  Jingyi Bai

    IPC分类号： G03F1/00

    CPC分类号： G03F7/11 ,  G03F7/0045 ,  G03F7/091

    摘要： A photo acid generator (PAG) or an acid is used to reduce resist scumming and footing. Diffusion of acid from photoresist into neighbors causes a decreased acid level, and thus causes resist scumming. An increased acid layer beneath the resist prevents acid diffusion. In one embodiment, the increased acid layer is a layer of spun-on acid or PAG dissolved in aqueous solution. In another embodiment, the increased acid layer is a hard mask material with a PAG or an acid mixed into the material. The high acid content inhibits the diffusion of acid from the photoresist into neighboring layers, and thus substantially reduces photoresist scumming and footing.

    摘要翻译： 使用光酸产生剂（PAG）或酸来降低抗污垢和基底。 酸从光致抗蚀剂扩散到邻居会导致酸水平降低，从而导致抗污垢浮渣。 抗蚀剂下面的增加的酸层防止酸扩散。 在一个实施方案中，增加的酸层是溶解在水溶液中的纺丝酸或PAG层。 在另一个实施方案中，增加的酸层是具有混合到该材料中的PAG或酸的硬掩模材料。 高酸含量抑制酸从光致抗蚀剂扩散到相邻层中，从而基本上减少光致抗蚀剂的浮渣和基底。

    Method of forming interconnect structure with interlayer dielectric
    64.
    发明授权
    Method of forming interconnect structure with interlayer dielectric 有权
    用层间电介质形成互连结构的方法

    公开(公告)号：US07279414B1

    公开(公告)日：2007-10-09

    申请号：US09293188

    申请日：1999-04-16

    申请人： Zhiping Yin ,  Mark Jost

    发明人： Zhiping Yin ,  Mark Jost

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76849 ,  H01L21/76801 ,  H01L21/76867

    摘要： The present invention relates to the formation of an ILD layer while preventing or reducing oxidation of the upper surface of a metallic interconnect. Avoidance of oxidation of the upper surface of a metallic interconnect is achieved according to the present invention by passivating the exposed upper surface of the metallic interconnect prior to formation of the ILD. In order to avoid the oxidation of an upper surface of an interconnect during the formation of an ILD layer, an in situ passivation of the upper surface of the interconnect, immediately prior to or simultaneously with the formation of the ILD layer avoids the problems of the prior art.

    摘要翻译： 本发明涉及ILD层的形成，同时防止或减少金属互连的上表面的氧化。 根据本发明，通过在形成ILD之前钝化金属互连的暴露的上表面来实现避免金属互连的上表面的氧化。 为了避免在形成ILD层期间互连的上表面的氧化，在形成ILD层之前或同时形成ILD层的互连的上表面的原位钝化避免了以下问题： 现有技术

    Compositions of matter and barrier layer compositions
    65.
    发明授权
    Compositions of matter and barrier layer compositions 有权
    物质和阻挡层组合物的组成

    公开(公告)号：US07279118B2

    公开(公告)日：2007-10-09

    申请号：US10776553

    申请日：2004-02-10

    申请人： Weimin Li ,  Zhiping Yin

    发明人： Weimin Li ,  Zhiping Yin

    IPC分类号： C01B21/082

    CPC分类号： H01L21/76834 ,  H01L21/3185 ,  H01L21/76801 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In one aspect, the invention encompasses a semiconductor processing method wherein a conductive copper-containing material is formed over a semiconductive substrate and a second material is formed proximate the conductive material. A barrier layer is formed between the conductive material and the second material. The barrier layer comprises a compound having silicon chemically bonded to both nitrogen and an organic material. In another aspect, the invention encompasses a composition of matter comprising silicon chemically bonded to both nitrogen and an organic material. The nitrogen is not bonded to carbon. In yet another aspect, the invention encompasses a semiconductor processing method. A semiconductive substrate is provided and a layer is formed over the semiconductive substrate. The layer comprises a compound having silicon chemically bonded to both nitrogen and an organic material.

    摘要翻译： 一方面，本发明包括一种半导体处理方法，其中在半导体衬底上形成导电含铜材料，并且在导电材料附近形成第二材料。 在导电材料和第二材料之间形成阻挡层。 阻挡层包括具有与氮和有机材料化学键合的硅的化合物。 在另一方面，本发明包括包含与氮和有机材料化学键合的硅的物质组合物。 氮不与碳结合。 在另一方面，本发明包括半导体处理方法。 提供半导体衬底并且在半导体衬底上形成层。 该层包括具有与氮和有机材料化学键合的硅的化合物。

    PITCH REDUCED PATTERNS RELATIVE TO PHOTOLITHOGRAPHY FEATURES
    66.
    发明申请
    PITCH REDUCED PATTERNS RELATIVE TO PHOTOLITHOGRAPHY FEATURES 失效
    相对于光刻特征的PITCH减少图案

    公开(公告)号：US20070161251A1

    公开(公告)日：2007-07-12

    申请号：US11681027

    申请日：2007-03-01

    申请人： Luan Tran ,  William Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer Abatchev ,  Gurtej Sandhu ,  D. Durcan

    发明人： Luan Tran ,  William Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer Abatchev ,  Gurtej Sandhu ,  D. Durcan

    IPC分类号： H01L21/302

    CPC分类号： H01L21/0338 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3088

    摘要： Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.

    摘要翻译： 通过使用通过组合两个单独形成的图案形成的掩模蚀刻衬底来形成集成电路的不同尺寸的特征。 间距乘法用于形成第一图案的相对较小的特征以及用于形成第二图案的较大特征的常规光刻。 间距倍增通过对光致抗蚀剂进行图案化，然后将该图案蚀刻成无定形碳层来实现。 然后在无定形碳的侧壁上形成侧壁间隔物。 去除无定形碳，留下限定第一掩模图案的侧壁间隔物。 然后将底部抗反射涂层（BARC）沉积在间隔物周围以形成平坦表面，并且在BARC上形成光致抗蚀剂层。 接下来通过常规光刻法将光致抗蚀剂图案化以形成第二图案，然后将其转印到BARC。 通过第一图案和第二图案形成的组合图案被转印到下面的非晶硅层，并且图案经受碳带以去除BARC和光致抗蚀剂材料。 然后将组合图案转移到氧化硅层，然后转移到无定形碳掩模层。 具有不同尺寸特征的组合掩模图案然后通过无定形碳硬掩模层蚀刻到下面的衬底中。

    Antireflective coating for use during the manufacture of a semiconductor device
    69.
    发明申请
    Antireflective coating for use during the manufacture of a semiconductor device 审中-公开
    在制造半导体器件期间使用的抗反射涂层

    公开(公告)号：US20060220184A1

    公开(公告)日：2006-10-05

    申请号：US11214376

    申请日：2005-08-29

    申请人： Zhiping Yin ,  Gurtej Sandhu

    发明人： Zhiping Yin ,  Gurtej Sandhu

    IPC分类号： H01L23/58

    CPC分类号： H01L27/10888 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/76802 ,  H01L27/10811 ,  H01L27/10852 ,  H01L28/90

    摘要： An antireflective layer formed from boron-doped amorphous carbon may be removed using a process which is less likely to over etch a dielectric layer than conventional technology. This layer may be removed by exposing the layer to an oxygen plasma (i.e. an “ashing” process), preferably concurrently with the ashing and removal of an overlying photoresist layer. An inventive process which uses the inventive antireflective layer is also described.

    摘要翻译： 可以使用与常规技术相比不太可能过蚀刻电介质层的方法来去除由硼掺杂的非晶碳形成的抗反射层。 可以通过将层暴露于氧等离子体（即，“灰化”工艺），优选地与上覆的光致抗蚀剂层的灰化和去除同时地去除该层。 还描述了使用本发明的抗反射层的本发明的方法。

    Pitch reduced patterns relative to photolithography features
    70.
    发明申请
    Pitch reduced patterns relative to photolithography features 有权
    相对于光刻特征的间距减小

    公开(公告)号：US20060211260A1

    公开(公告)日：2006-09-21

    申请号：US11214544

    申请日：2005-08-29

    申请人： Luan Tran ,  William Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi (Jenny) Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer Abatchev ,  Gurtej Sandhu ,  D. Durcan

    发明人： Luan Tran ,  William Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi (Jenny) Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer Abatchev ,  Gurtej Sandhu ,  D. Durcan

    IPC分类号： H01L21/31

    CPC分类号： H01L21/0338 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3088

    摘要： Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.

    摘要翻译： 通过使用通过组合两个单独形成的图案形成的掩模蚀刻衬底来形成集成电路的不同尺寸的特征。 间距乘法用于形成第一图案的相对较小的特征以及用于形成第二图案的较大特征的常规光刻。 间距倍增通过对光致抗蚀剂进行图案化，然后将该图案蚀刻成无定形碳层来实现。 然后在无定形碳的侧壁上形成侧壁间隔物。 去除无定形碳，留下限定第一掩模图案的侧壁间隔物。 然后将底部抗反射涂层（BARC）沉积在间隔物周围以形成平坦表面，并且在BARC上形成光致抗蚀剂层。 接下来通过常规光刻法将光致抗蚀剂图案化以形成第二图案，然后将其转印到BARC。 通过第一图案和第二图案形成的组合图案被转印到下面的非晶硅层，并且图案经受碳带以去除BARC和光致抗蚀剂材料。 然后将组合图案转移到氧化硅层，然后转移到无定形碳掩模层。 具有不同尺寸特征的组合掩模图案然后通过无定形碳硬掩模层蚀刻到下面的衬底中。