公开(公告)号：US20170242614A1

公开(公告)日：2017-08-24

申请号：US15394621

申请日：2016-12-29

申请人： GOOGLE INC.

发明人： Santhosh RAO ,  Sameer NANDA ,  Vyacheslav Vladimirovich MALYUGIN ,  Luigi SEMENZATO ,  Aaron DURBIN ,  Keith Robert PFLEDERER ,  Hsiao-Heng Kelin LEE ,  Rahul Jagdish THAKUR

IPC分类号： G06F3/06

CPC分类号： G06F3/0638 ,  G06F3/0608 ,  G06F3/0656 ,  G06F3/0673 ,  G06F12/023 ,  G06F12/0804 ,  G06F2212/1044 ,  G06F2212/401 ,  H03M7/30 ,  H03M7/6011 ,  H03M7/6058

摘要： Systems, devices, and methods for managing fragmentation in hardware-assisted compression of data in physical computer memory which may result in reduced internal fragmentation. An example computer-implemented method comprises: providing, by a memory management program to compression hardware, a compression command including an address in physical computer memory of data to be compressed and a list of at least two available buffers for storing compressed data; using, by the compression hardware, the address included in the compression command to retrieve uncompressed data; compressing the uncompressed data; and selecting, by the compression hardware, from the list of at least two available buffers, at least two buffers for storing compressed data based on an amount of space that would remain if the compressed data were stored in the at least two buffers, wherein each of the at least two selected buffers differs in size from at least one other of the selected buffers.

公开(公告)号：US09740621B2

公开(公告)日：2017-08-22

申请号：US14716108

申请日：2015-05-19

申请人： QUALCOMM Incorporated

发明人： Mattheus Cornelis Antonius Adrianus Heddes ,  Natarajan Vaidhyanathan ,  Colin Beaton Verrilli

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F12/0875 ,  G06F12/0862 ,  G06F12/02 ,  G06F12/1009 ,  H03M7/30

CPC分类号： G06F12/0875 ,  G06F12/0246 ,  G06F12/0862 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/1056 ,  G06F2212/251 ,  G06F2212/401 ,  G06F2212/45 ,  G06F2212/602 ,  H03M7/30 ,  Y02D10/13

摘要： Memory controllers employing memory capacity and/or bandwidth compression with next read address prefetching, and related processor-based systems and methods are disclosed. In certain aspects, memory controllers are employed that can provide memory capacity compression. In certain aspects disclosed herein, a next read address prefetching scheme can be used by a memory controller to speculatively prefetch data from system memory at another address beyond the currently accessed address. Thus, when memory data is addressed in the compressed memory, if the next read address is stored in metadata associated with the memory block at the accessed address, the memory data at the next read address can be prefetched by the memory controller to be available in case a subsequent read operation issued by a central processing unit (CPU) has been prefetched by the memory controller.

公开(公告)号：US09740559B2

公开(公告)日：2017-08-22

申请号：US14925726

申请日：2015-10-28

申请人： Avago Technologies General IP (Singapore) Pte. Ltd.

发明人： Zhijun Zhao

IPC分类号： G06F11/10 ,  G11C29/52 ,  H03M13/11

CPC分类号： G06F11/1068 ,  G06F11/1012 ,  G06F2212/401 ,  G06F2212/403 ,  H03M7/00 ,  H03M13/1102 ,  H03M13/1111 ,  H03M13/6588

摘要： Embodiments are related to systems and methods for data storage, and more particularly to systems and methods for storing data to and accessing data from a flash memory.

公开(公告)号：US09727479B1

公开(公告)日：2017-08-08

申请号：US14502244

申请日：2014-09-30

申请人： EMC Corporation

发明人： Philippe Armangau ,  Vasily Olegovich Zalunin ,  Rustem Rafikov ,  Christopher A. Seibel

IPC分类号： G06F12/08 ,  G06F12/0891 ,  G06F12/0866

CPC分类号： G06F12/0891 ,  G06F12/0866 ,  G06F12/1009 ,  G06F12/123 ,  G06F2212/1024 ,  G06F2212/281 ,  G06F2212/401 ,  G06F2212/69

摘要： Techniques are described for compressing cache pages from an LRU (Least-Recently-Used) queue so that data takes longer to age off and be removed from the cache. This increases the likelihood that data will be available within the cache upon subsequent re-access, reducing the need for costly disk accesses due to cache misses.

公开(公告)号：US09720617B2

公开(公告)日：2017-08-01

申请号：US14728971

申请日：2015-06-02

申请人： Apple Inc.

发明人： Andrew D. Myrick ,  Lionel D. Desai ,  Joseph Sokol, Jr.

IPC分类号： G06F13/00 ,  G06F3/06 ,  G06F12/08

CPC分类号： G06F3/0643 ,  G06F3/0604 ,  G06F3/0632 ,  G06F3/0679 ,  G06F12/08 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/109 ,  G06F2212/1016 ,  G06F2212/401

摘要： In one embodiment, when a secondary application on an electronic device is selected for deactivation, the memory associated with the application can be gathered, compacted and compressed into a memory freezer file. The memory freezer file can be stored in non-volatile memory with a reduced storage footprint compared to a memory stored in a conventional swap file. When the selected application is to be reactivated, the compressed memory in the memory freezer file can be quickly restored to process memory.

公开(公告)号：US20170185532A1

公开(公告)日：2017-06-29

申请号：US14998054

申请日：2015-12-24

申请人： Intel Corporation

发明人： David M. Durham ,  Siddhartha Chhabra ,  Sergej Deutsch ,  Men Long ,  Alpa T. Narendra Trivedi

IPC分类号： G06F12/14 ,  G06F11/10

CPC分类号： G06F11/1004 ,  G06F12/0886 ,  G06F12/1408 ,  G06F21/00 ,  G06F21/79 ,  G06F2212/401 ,  H04L9/0858 ,  H04L9/304

摘要： Apparatus, systems, and/or methods may provide for identifying unencrypted data including a plurality of bits, wherein the unencrypted data may be encrypted and stored in memory. In addition, a determination may be made as to whether the unencrypted data includes a random distribution of the plurality of bits, for example based on a compressibility function. An integrity action may be implemented when the unencrypted data includes a random distribution of the plurality of bits, which may include error correction including a modification to ciphertext of the unencrypted data. Independently of error correction, a diffuser may generate intermediate and final ciphertext. In addition, a key and/or a tweak may be derived for a location in the memory. Moreover, an integrity value may be generated (e.g., as a copy) from a portion of the unencrypted data, and/or stored in a slot of an integrity check line based on the location.

公开(公告)号：US20170177505A1

公开(公告)日：2017-06-22

申请号：US14975588

申请日：2015-12-18

申请人： Intel Corporation

发明人： ABHISHEK BASAK ,  SIDDHARTHA CHHABRA ,  JUNGJU OH ,  DAVID M. DURHAM

IPC分类号： G06F12/14 ,  H04L9/06 ,  G06F3/06 ,  G06F12/12 ,  G06F12/08

CPC分类号： G06F21/79 ,  G06F3/0623 ,  G06F3/0661 ,  G06F3/0673 ,  G06F7/724 ,  G06F12/0886 ,  G06F12/0891 ,  G06F12/124 ,  G06F12/1408 ,  G06F2212/1052 ,  G06F2212/401 ,  G06F2212/402 ,  G06F2212/60 ,  G06F2212/70 ,  H03M13/15 ,  H04L9/0637 ,  H04L9/3242 ,  H04N19/463 ,  H04N19/93

摘要： Examples include techniques for compressing counter values included in cryptographic metadata. In some examples, a cache line to fill a cache included in on-die processor memory may be received. The cache arranged to store cryptographic metadata. The cache line includes a counter value generated by a counter. The counter value to serve as version information for a memory encryption scheme to write a data cache line to a memory location of an off-die memory. In some examples, the counter value is compressed based on whether the counter value includes a pattern that matches a given pattern and is then stored to the cache. In some examples, a compression aware and last recently used (LRU) scheme is used to determine whether to evict cryptographic metadata from the cache.

公开(公告)号：US20170123978A1

公开(公告)日：2017-05-04

申请号：US14925922

申请日：2015-10-28

申请人： NVIDIA CORPORATION

发明人： Praveen KRISHNAMURTHY ,  Peter B. HOLMQUIST ,  Wishwesh GANDHI ,  Timothy PURCELL ,  Karan MEHRA ,  Lacky SHAH

IPC分类号： G06F12/08 ,  G06F3/06

CPC分类号： G06F12/0802 ,  G06F3/0608 ,  G06F3/064 ,  G06F3/0673 ,  G06F12/0842 ,  G06F12/0844 ,  G06F12/0848 ,  G06F12/0851 ,  G06F12/0853 ,  G06F12/0895 ,  G06F2212/1016 ,  G06F2212/401 ,  G06F2212/608

摘要： In one embodiment of the present invention a cache unit organizes data stored in an attached memory to optimize accesses to compressed data. In operation, the cache unit introduces a layer of indirection between a physical address associated with a memory access request and groups of blocks in the attached memory. The layer of indirection—virtual tiles—enables the cache unit to selectively store compressed data that would conventionally be stored in separate physical tiles included in a group of blocks in a single physical tile. Because the cache unit stores compressed data associated with multiple physical tiles in a single physical tile and, more specifically, in adjacent locations within the single physical tile, the cache unit coalesces the compressed data into contiguous blocks. Subsequently, upon performing a read operation, the cache unit may retrieve the compressed data conventionally associated with separate physical tiles in a single read operation.

公开(公告)号：US20170123900A1

公开(公告)日：2017-05-04

申请号：US14925726

申请日：2015-10-28

申请人： Avago Technologies General IP (Singapore) Pte. Ltd.

发明人： Zhijun Zhao

IPC分类号： G06F11/10 ,  H03M13/11 ,  G11C29/52

CPC分类号： G06F11/1068 ,  G06F11/1012 ,  G06F2212/401 ,  G06F2212/403 ,  H03M7/00 ,  H03M13/1102 ,  H03M13/1111 ,  H03M13/6588

摘要： Embodiments are related to systems and methods for data storage, and more particularly to systems and methods for storing data to and accessing data from a flash memory.

公开(公告)号：US20170123897A1

公开(公告)日：2017-05-04

申请号：US14994078

申请日：2016-01-12

申请人： QUALCOMM INCORPORATED

发明人： Nhon Quach ,  Mainak Biswas ,  Pranjal Bhuyan ,  Jeffrey Shabel ,  Robert Hardacker ,  Rahul Gulati ,  Mattheus Heddes

IPC分类号： G06F11/10 ,  G06F12/08

CPC分类号： G06F11/1064 ,  G06F11/1012 ,  G06F12/08 ,  G06F12/0888 ,  G06F2212/1032 ,  G06F2212/1044 ,  G06F2212/1056 ,  G06F2212/281 ,  G06F2212/401 ,  G06F2212/466

摘要： Systems and methods are disclosed for error correction control (ECC) for a memory device comprising a data portion and an ECC portion, the memory device coupled to a system on a chip (SoC). The SoC includes an ECC cache. On receipt of a request to write a line of data to the memory, a determination is made if the data is compressible. If so, the data line is compressed. ECC bits are generated for the compressed or uncompressed data line. A determination is made if an ECC cache line is associated with the received data line. If the data line is compressible, the ECC bits are appended to the compressed data line and the appended data line is stored in the data portion of the memory. Otherwise, the ECC bits are stored in the ECC cache and the data line is stored in the data portion of the memory.