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    Apparatus and method for injecting spin echo micro-operations in a quantum processor
    61.
    发明授权
    Apparatus and method for injecting spin echo micro-operations in a quantum processor 有权

    公开(公告)号：US11704588B2

    公开(公告)日：2023-07-18

    申请号：US16144963

    申请日：2018-09-27

    Applicant: Intel Corporation

    Inventor： Xiang Zou ,  Justin Hogaboam

    IPC: G06N10/70 ,  G06F9/30 ,  G06F9/22 ,  G06F9/38

    CPC classification number: G06N10/70 ,  G06F9/22 ,  G06F9/3017 ,  G06F9/30101 ,  G06F9/3877

    Abstract: Apparatus and method for injected spin echo sequences in a quantum processor. For example, one embodiment of a processor includes a decoder to decode quantum instructions to generate quantum microoperations (uops) and to decode non-quantum instructions to generate non-quantum uops, execution circuitry to execute the quantum uops and non-quantum uops, and a corrective sequence data structure to identify and/or store corrective sets of uops for one or more of the quantum instructions. The decoder is to query the corrective sequence data structure upon receiving a first quantum instruction to determine if one or more corrective uops exist, and if the one or more corrective uops exist, the decoder is to submit the one or more corrective uops for execution by the execution circuitry.

    Guest-specific microcode
    65.
    发明授权
    Guest-specific microcode 有权

    公开(公告)号：US09747118B2

    公开(公告)日：2017-08-29

    申请号：US12349307

    申请日：2009-01-06

    Applicant: Richard L. Maliszewski ,  James P. Held ,  Daniel Baumberger

    Inventor： Richard L. Maliszewski ,  James P. Held ,  Daniel Baumberger

    IPC: G06F9/30 ,  G06F9/455 ,  G06F9/22

    CPC classification number: G06F9/45533 ,  G06F9/22 ,  G06F9/30174 ,  G06F9/30189

    Abstract: Embodiments of apparatuses, methods, and systems for modifying the behavior of a guest installed to run within a VM are disclosed. In one embodiment, an apparatus includes virtualization logic, first storage, second storage, decode logic, and multiplexing logic. The virtualization logic is to provide a mode in which to operate a virtual machine. The first storage is to store a first plurality of micro-instructions to control the apparatus. The second storage is to store a second plurality of micro-instructions to control the apparatus. The decode logic is to decode a macro-instruction into one of a first plurality and a second plurality of micro-instructions. The multiplexing logic is to cause the macro-instruction to be decoded into the second plurality of micro-instructions instead of the first plurality of micro-instructions only when issued from the virtual machine.

    Load multiple and store multiple instructions in a microprocessor that emulates banked registers
    69.
    发明授权
    Load multiple and store multiple instructions in a microprocessor that emulates banked registers 有权
    加载多个并将多个指令存储在模拟存储寄存器的微处理器中

    公开(公告)号：US09176733B2

    公开(公告)日：2015-11-03

    申请号：US13413314

    申请日：2012-03-06

    Applicant: G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker

    Inventor： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker

    IPC: G06F9/30 ,  G06F9/22 ,  G06F12/08

    CPC classification number: G06F9/22 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F12/0875

    Abstract: A microprocessor supports an instruction set architecture that specifies: processor modes, architectural registers associated with each mode, and a load multiple instruction that instructs the microprocessor to load data from memory into specified ones of the registers. Direct storage holds data associated with a first portion of the registers and is coupled to an execution unit to provide the data thereto. Indirect storage holds data associated with a second portion of the registers and cannot directly provide the data to the execution unit. Which architectural registers are in the first and second portions varies dynamically based upon the current processor mode. If a specified register is currently in the first portion, the microprocessor loads data from memory into the direct storage, whereas if in the second portion, the microprocessor loads data from memory into the direct storage and then stores the data from the direct storage to the indirect storage.

    Abstract translation: 微处理器支持指令集架构，其指定：处理器模式，与每种模式相关联的架构寄存器，以及指令微处理器将数据从存储器加载到指定寄存器中的加载多指令。 直接存储保持与寄存器的第一部分相关联的数据，并且耦合到执行单元以向其提供数据。 间接存储保存与寄存器的第二部分相关联的数据，并且不能将数据直接提供给执行单元。 第一和第二部分中的哪些架构寄存器基于当前的处理器模式动态变化。 如果指定的寄存器当前位于第一部分，则微处理器将数据从存储器加载到直接存储器中，而如果在第二部分中，微处理器将数据从存储器加载到直接存储器中，然后将数据从直接存储器存储到 间接存储。

    LOCAL POWER GATE (LPG) INTERFACES FOR POWER-AWARE OPERATIONS
    70.
    发明申请
    LOCAL POWER GATE (LPG) INTERFACES FOR POWER-AWARE OPERATIONS 有权
    本地电力门（LPG）接口，用于功率操作

    公开(公告)号：US20150277532A1

    公开(公告)日：2015-10-01

    申请号：US14225612

    申请日：2014-03-26

    Applicant: MICHAEL MISHAELI ,  RON GABOR ,  ROBERT C. VALENTINE ,  ALEX GERBER ,  ZEEV SPERBER

    Inventor： MICHAEL MISHAELI ,  RON GABOR ,  ROBERT C. VALENTINE ,  ALEX GERBER ,  ZEEV SPERBER

    IPC: G06F1/32

    CPC classification number: G06F1/3206 ,  G06F1/3287 ,  G06F9/22 ,  Y02D10/171

    Abstract: Technologies for local power gate (LPG) interfaces for power-aware operations are described. A processor includes locally-gated circuitry of a core, main core circuitry of the core, the main core, and local power gate (LPG) hardware. The LPG hardware is to power gate the locally-gated circuitry according to local power states of the LPG hardware. The main core decodes a first instruction of a set of instructions to perform a first power-aware operation of a specified length, including computing an execution code path for execution. The main core monitors a current local power state of the LPG hardware, selects one of the code paths based on the current local power state, the specified length, and a specified threshold, and issues a hint to the LPG hardware to power up the locally-gated circuitry and continues execution of the first power-aware operation without waiting for the locally-gated circuitry to be powered up.

    Abstract translation: 描述了用于功率感知操作的本地电源门（LPG）接口的技术。 处理器包括核心的本地门控电路，核心的主核心电路，主核心和本地电源门（LPG）硬件。 LPG硬件根据LPG硬件的本地电源状态为本地门控电路供电。 主核心解码一组指令的第一指令以执行指定长度的第一功率感知操作，包括计算用于执行的执行代码路径。 主核心监控LPG硬件的当前本地电源状态，根据当前本地电源状态，指定长度和指定的阈值选择其中一条代码路径，并向LPG硬件发出提示，以启动本地 并且继续执行第一功率感知操作，而不等待本地门控电路被加电。

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