公开(公告)号：US09325340B2

公开(公告)日：2016-04-26

申请号：US14475180

申请日：2014-09-02

申请人： NXP B.V.

发明人： Burak Gonen ,  Fabio Sebastiano ,  Kofi Afolabi Anthony Makinwa ,  Robert Hendrikus Margaretha van Veldhoven

IPC分类号： H03M1/12 ,  H03M1/14 ,  H03M3/00 ,  H03M1/38

CPC分类号： H03M1/14 ,  H03M1/066 ,  H03M1/38 ,  H03M1/42 ,  H03M3/458

摘要： An efficient analog to digital converter is disclosed. The efficient analog to digital converter includes a coarse analog to digital converter coupled to an input analog signal. The coarse analog to digital converter is configured to provide an approximate digital representation of the input analog signal. The efficient analog to digital converter also includes a fine analog to digital converter coupled to the input analog signal. The output of the coarse analog to digital converter is coupled to the fine analog to digital converter. The fine analog to digital converter is configured to set input range of the fine analog to digital converter as a function of the output of the coarse analog to digital converter.

摘要翻译： 公开了一种高效的模数转换器。 有效的模数转换器包括耦合到输入模拟信号的粗模数转换器。 粗略模数转换器被配置为提供输入模拟信号的近似数字表示。 高效的模数转换器还包括耦合到输入模拟信号的精细模数转换器。 粗略模数转换器的输出端连接到精细模数转换器。 精细模数转换器被配置为根据粗略模数转换器的输出设置精细模数转换器的输入范围。

公开(公告)号：US20160065231A1

公开(公告)日：2016-03-03

申请号：US14475180

申请日：2014-09-02

申请人： NXP B.V.

发明人： Burak Gonen ,  Fabio Sebastiano ,  Kofi Afolabi Anthony Makinwa ,  Robert Hendrikus Margaretha van Veldhoven

IPC分类号： H03M1/14 ,  H03M1/38 ,  H03M3/00

CPC分类号： H03M1/14 ,  H03M1/066 ,  H03M1/38 ,  H03M1/42 ,  H03M3/458

摘要： An efficient analog to digital converter is disclosed. The efficient analog to digital converter includes a coarse analog to digital converter coupled to an input analog signal. The coarse analog to digital converter is configured to provide an approximate digital representation of the input analog signal. The efficient analog to digital converter also includes a fine analog to digital converter coupled to the input analog signal. The output of the coarse analog to digital converter is coupled to the fine analog to digital converter. The fine analog to digital converter is configured to set input range of the fine analog to digital converter as a function of the output of the coarse analog to digital converter.

摘要翻译： 公开了一种高效的模数转换器。 有效的模数转换器包括耦合到输入模拟信号的粗模数转换器。 粗略模数转换器被配置为提供输入模拟信号的近似数字表示。 高效的模数转换器还包括耦合到输入模拟信号的精细模数转换器。 粗略模数转换器的输出端连接到精细模数转换器。 精细模数转换器被配置为根据粗略模数转换器的输出设置精细模数转换器的输入范围。

公开(公告)号：US09041584B2

公开(公告)日：2015-05-26

申请号：US14016948

申请日：2013-09-03

申请人： Silicon Laboratories Inc.

发明人： Xiaodong Wang ,  Shouli Yan ,  Axel Thomsen

IPC分类号： H03M1/12 ,  H03M1/42 ,  H03M1/38 ,  H03M1/40

CPC分类号： H03M1/42 ,  H03M1/0692 ,  H03M1/188 ,  H03M1/38 ,  H03M1/403 ,  H03M1/466

摘要： A method includes receiving a differential voltage signal at first and second inputs of a comparator and selectively providing the differential voltage signal to one of a first conversion path and a second conversion path of the comparator during a conversion phase to determine a digital value corresponding to the differential voltage signal. The first and second conversion paths including first and second pluralities of gain stages, respectively. The method further includes coupling the selected one of the first conversion path and the second conversion path to an output to provide the digital value.

摘要翻译： 一种方法包括在比较器的第一和第二输入处接收差分电压信号，并且在转换阶段期间选​​择性地将差分电压信号提供给比较器的第一转换路径和第二转换路径中的一个，以确定对应于 差分电压信号。 第一和第二转换路径分别包括第一和第二多个增益级。 该方法还包括将所选择的第一转换路径和第二转换路径中的一个耦合到输出以提供数字值。

公开(公告)号：US20150124137A1

公开(公告)日：2015-05-07

申请号：US14396912

申请日：2013-05-08

申请人： Sony Corporation

发明人： Mamoru Sato ,  Yusuke Oike ,  Hiroyuki Iwaki

IPC分类号： H04N5/3745 ,  H03M1/42 ,  H03M1/08 ,  H04N5/363 ,  H03M1/12

CPC分类号： H04N5/37455 ,  H03M1/08 ,  H03M1/0845 ,  H03M1/123 ,  H03M1/1245 ,  H03M1/182 ,  H03M1/42 ,  H03M1/56 ,  H04N5/3575 ,  H04N5/363 ,  H04N5/378

摘要： The present invention is to provide an A/D conversion device, a solid-state image-capturing device, and an electronic device capable of removing fixed pattern noise, capable of preventing an image from being corrupted, capable of generating an appropriate carry signal during bit shift, and capable of avoiding bit inconsistency even when the frequency of the carry signal increases due to the bit shift. A reading unit includes a comparator configured to compare the analog signal potential with a reference signal of which slope is variable, a counter latch unit capable of AD conversion based on processing according to the output of the comparator, and a bit shift function unit capable of bit-shifting the digital data obtained by the counter latch unit, and when digital Correlated Double Sampling (CDS) is performed with a first signal and a second signal having different bit precisions obtained from the comparison with reference signals of different slopes, the bit shift function unit bit-shifts the first signal or the second signal.

摘要翻译： 本发明提供一种A / D转换装置，固态图像捕获装置和能够消除能够防止图像被破坏的固定图案噪声的电子装置，其能够在 并且即使当进位信号的频率由于位移而增加时，也能够避免位不一致。 读取单元包括：比较器，被配置为将模拟信号电位与斜率可变的参考信号进行比较;基于根据比较器的输出的处理能够进行AD转换的计数器锁存单元;以及位移功能单元， 对由计数器锁存单元获得的数字数据进行位移位，并且当使用从与不同斜率的参考信号的比较获得的具有不同位精度的第一信号和第二信号执行数字相关双采样（CDS）时，位移 功能单元对第一信号或第二信号进行位移位。

公开(公告)号：US20130201043A1

公开(公告)日：2013-08-08

申请号：US13369093

申请日：2012-02-08

申请人： Ark-Chew WONG ,  Olivier Jacques NYS ,  Jonathan MULLER

发明人： Ark-Chew WONG ,  Olivier Jacques NYS ,  Jonathan MULLER

IPC分类号： H03M1/34 ,  H03M1/00

CPC分类号： H03M1/125 ,  H03M1/42

摘要： Examples are provided for converting an analog signal to a digital output signal using serial-ripple analog-to-digital conversion (ADC). An ADC circuit may include conversion stages coupled in series. Each conversion stage may generate a bit for the digital output signal. A data latch may receive bits for the digital output signal from the conversion stages and to provide the digital output signal based on the bits. A conversion stage may include a comparator circuit and a multiplexer circuit. The comparator circuit may compare a sampled input signal with a reference signal and to generate the associated bit of the digital output signal based on a result of the comparison. The multiplexer circuit may provide an associated reference signal to a comparator circuit of a next conversion stage, where the next conversion stage is subsequent to the conversion stage.

摘要翻译： 提供了使用串行纹波模数转换（ADC）将模拟信号转换为数字输出信号的示例。 ADC电路可以包括串联耦合的转换级。 每个转换级可以产生数字输出信号的位。 数据锁存器可以接收来自转换级的数字输出信号的位，并且基于位提供数字输出信号。 转换级可以包括比较器电路和多路复用器电路。 比较器电路可以将采样的输入信号与参考信号进行比较，并且基于比较的结果产生数字输出信号的相关位。 多路复用器电路可以向下一个转换级的比较器电路提供相关联的参考信号，其中下一个转换级在转换级之后。

公开(公告)号：US20120092202A1

公开(公告)日：2012-04-19

申请号：US13060720

申请日：2009-09-01

申请人： Nikolaos Petrellis ,  Michael Birbas ,  John Kikidis

发明人： Nikolaos Petrellis ,  Michael Birbas ,  John Kikidis

IPC分类号： H03M1/12

CPC分类号： H03M1/368 ,  H03M1/146 ,  H03M1/164 ,  H03M1/366 ,  H03M1/42

摘要： An analog to digital converter for converting an initial analog signal into a digital signal comprising at least one electronic module with an input, a first output, and a second output, which module generates from an analog input signal: a first output signal, which first output signal in terms of multiples of a predetermined amount of current or voltage, such as 1 uA or 1 mV, is substantially equal to the integer quotient of division of the input signal by a number or comprises a plurality of signals which if combined are substantially equal to the integer quotient of division of the input signal in terms of multiples of a predetermined amount of current or voltage, and a second output signal which in terms of multiples of a predetermined amount of current or voltage, such as 1 uA or 1 mV, is substantially equal to the remainder of the division, the analog to digital converter also comprising a further analog to digital converter for converting the second output signal into a digital signal, wherein the further analog to digital converter is connected the at least one module and the module is configured so that in use when the analog input signal connects through the input the first output signal connects through the first output, and the second output signal connects through the second output into the further analog to digital converter.

摘要翻译： 一种模数转换器，用于将初始模拟信号转换成数字信号，该数字信号包括至少一个电子模块，该输入，第一输出和第二输出由模拟输入信号产生：第一输出信号，第一输出信号 输出信号以预定量的电流或电压（例如1uA或1mV）的倍数基本上等于输入信号除数的整数商，或包括多个信号，如果被组合为基本上 等于以预定量的电流或电压的倍数的输入信号的除法的整数商和以预定量的电流或电压（例如1uA或1mV）的倍数的第二输出信号 ，基本上等于除法的剩余部分，模数转换器还包括另外的模数转换器，用于将第二输出信号转换为数字 信号，其中所述另外的模数转换器连接到所述至少一个模块，并且所述模块被配置为使得当模拟输入信号通过输入连接时，第一输出信号通过第一输出连接，并且第二输出信号连接 通过第二个输出进一步的模数转换器。

公开(公告)号：US20090185613A1

公开(公告)日：2009-07-23

申请号：US12335493

申请日：2008-12-15

申请人： Oscar E. Agazzi ,  Diego E. Crivelli ,  Hugo S. Carrer ,  Mario R. Hueda ,  German C. Luna ,  Carl Grace

发明人： Oscar E. Agazzi ,  Diego E. Crivelli ,  Hugo S. Carrer ,  Mario R. Hueda ,  German C. Luna ,  Carl Grace

IPC分类号： H04L27/01

CPC分类号： H03M1/1042 ,  H03M1/0626 ,  H03M1/0692 ,  H03M1/0695 ,  H03M1/1215 ,  H03M1/181 ,  H03M1/42 ,  H03M1/44 ,  H04L1/0054 ,  H04L1/0071 ,  H04L7/0004 ,  H04L7/0062 ,  H04L7/0083 ,  H04L7/0087 ,  H04L25/0204 ,  H04L25/03038

摘要： A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

摘要翻译： 接收机（例如，用于10G光纤通信链路）包括耦合到多通道均衡器的交错ADC，其可以为交错ADC内的不同ADC通道提供不同的均衡。 也就是说，多通道均衡器可以补偿信道相关的损伤。 在一种方法中，多信道均衡器是耦合到维特比解码器（例如滑块维特比解码器（SBVD））的前馈均衡器（FFE）; 并且使用LMS算法适配维特比解码器的FFE和/或信道估计器。

公开(公告)号：US06700523B2

公开(公告)日：2004-03-02

申请号：US09983658

申请日：2001-10-25

申请人： Takashi Konno

发明人： Takashi Konno

IPC分类号： H03M134

CPC分类号： H03M1/42

摘要： An A/D converter includes first to Nth stages of A/D conversion units, which are connected in series, each A/D conversion unit converting an analog input signal into a digital output signal. Each of the A/D conversion units includes a) a sample-and-hold circuit, which holds an analog input signal; b) a selector which selects one from a plurality of reference voltage signals in accordance with a digital output signal outputted from the one stage preceding A/D conversion unit; and c) a comparator which compares an output signal supplied from the sample-and-hold circuit with the reference voltage signal selected by the selector.

摘要翻译： A / D转换器包括串联连接的A / D转换单元的第一至第N级，每个A / D转换单元将模拟输入信号转换为数字输出信号。 每个A / D转换单元包括a）保持模拟输入信号的采样和保持电路; b）选择器，其根据从一级前一A / D转换单元输出的数字输出信号从多个参考电压信号中选择一个; 以及c）将从采样保持电路提供的输出信号与由选择器选择的参考电压信号进行比较的比较器。

公开(公告)号：US06333709B2

公开(公告)日：2001-12-25

申请号：US09741197

申请日：2000-12-21

申请人： Yoshihiro Miyamoto

发明人： Yoshihiro Miyamoto

IPC分类号： H03M112

CPC分类号： G06F7/5013 ,  G06F2207/482 ,  H03K19/0813 ,  H03K19/23 ,  H03M1/129 ,  H03M1/144 ,  H03M1/145 ,  H03M1/403 ,  H03M1/42 ,  H03M1/46 ,  H03M1/60 ,  H03M1/667 ,  H03M1/68

摘要： According to the present invention, various logic circuits, AD converters, DA converters and counter circuits can be constituted with a small number of transistors by employing a capacitive coupling circuit. An analog/digital converter comprises: an input terminal, for which analog input is provided; an output terminal of N (N is a plural number) bits, for which binary output is provided; and N unit circuits arranged in parallel, each including an input capacitor having one electrode connected to the input terminal, a first inverter connected to the other electrode of the input capacitor, and a second inverter connected to the first inverter, wherein outputs of the second inverters of the unit circuits are respectively provided for the output terminals, wherein inverted outputs of the outputs for the unit circuits are fed back via feedback capacitors to respective input terminals of the first inverters of the unit circuits corresponding to lower bits, and wherein a capacitance of the feedback capacitor, which corresponds to the inverted output of the M-th (M is an integer) unit circuit from the most significant bit, is ½M times a capacitance of the input capacitor of the unit circuit that is fed back.

摘要翻译： 根据本发明，通过采用电容耦合电路，各种逻辑电路，AD转换器，DA转换器和计数器电路可以由少量晶体管构成。 一种模拟/数字转换器，包括：输入端，为其提供模拟输入; N（N是多个）位的输出端，提供二进制输出; 和N个单位电路，每个均包括一个输入电容器，该输入电容器具有连接到输入端子的一个电极，连接到输入电容器的另一个电极的第一反相器和连接到第一反相器的第二反相器，其中第二个 单元电路的逆变器分别设置用于输出端子，其中用于单位电路的输出的反相输出通过反馈电容器反馈到对应于低位的单元电路的第一反相器的相应输入端子，并且其中电容 对应于来自最高有效位的第M（M为整数）单位电路的反相输出的反馈电容是反馈的单位电路的输入电容器的电容的1/2倍。

公开(公告)号：US6043675A

公开(公告)日：2000-03-28

申请号：US888900

申请日：1997-07-07

申请人： Yoshihiro Miyamoto

发明人： Yoshihiro Miyamoto

IPC分类号： H03M1/44 ,  G06F7/50 ,  H03K5/08 ,  H03K19/08 ,  H03K19/23 ,  H03M1/12 ,  H03M1/14 ,  H03M1/40 ,  H03M1/42 ,  H03M1/46 ,  H03M1/60 ,  H03M1/66 ,  H03M1/68 ,  H03M1/74 ,  H03K19/20

CPC分类号： G06F7/5013 ,  H03K19/0813 ,  H03K19/23 ,  H03M1/129 ,  H03M1/144 ,  H03M1/145 ,  H03M1/403 ,  H03M1/42 ,  H03M1/46 ,  H03M1/60 ,  H03M1/667 ,  H03M1/68 ,  G06F2207/482

摘要： According to the present invention, various logic circuits, AD converters, DA converters and counter circuits can be constituted with a small number of transistors by employing a capacitive coupling circuit. An analog/digital converter comprises: an input terminal, for which analog input is provided; an output terminal of N (N is a plural number) bits, for which binary output is provided; and N unit circuits arranged in parallel, each including an input capacitor having one electrode connected to the input terminal, a first inverter connected to the other electrode of the input capacitor, and a second inverter connected to the first inverter, wherein outputs of the second inverters of the unit circuits are respectively provided for the output terminals, wherein inverted outputs of the outputs for the unit circuits are fed back via feedback capacitors to respective input terminals of the first inverters of the unit circuits corresponding to lower bits, and wherein a capacitance of the feedback capacitor, which corresponds to the inverted output of the M-th (M is an integer) unit circuit from the most significant bit, is 1/2.sup.M times a capacitance of the input capacitor of the unit circuit that is fed back.

摘要翻译： 根据本发明，通过采用电容耦合电路，各种逻辑电路，AD转换器，DA转换器和计数器电路可以由少量晶体管构成。 一种模拟/数字转换器，包括：输入端，为其提供模拟输入; N（N是多个）位的输出端，提供二进制输出; 和N个单位电路，每个均包括一个输入电容器，该输入电容器具有连接到输入端子的一个电极，连接到输入电容器的另一个电极的第一反相器和连接到第一反相器的第二反相器，其中第二个 单元电路的逆变器分别设置用于输出端子，其中用于单位电路的输出的反相输出通过反馈电容器反馈到对应于低位的单元电路的第一反相器的相应输入端子，并且其中电容 对应于来自最高有效位的第M（M为整数）单位电路的反相输出的反馈电容为+ E，fra 1/2 + EE M倍， 反馈的单元电路。