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公开(公告)号：US09762252B2
公开(公告)日：2017-09-12
申请号：US15022349
申请日：2013-09-16
CPC分类号： H03L7/0991 , H03L7/093 , H03L7/099 , H03L7/18 , H03L2207/06 , H03L2207/50
摘要： Methods and systems for a digitally controlled oscillator may comprise, for example, an all-digital all digital phase locked loop (ADPLL) for generating an output clock signal from a reference clock signal, the ADPLL comprising a thermometer pulse coder comprising a plurality of frequency control word signal lines. the thermometer pulse coder may be configured to generate a frequency control word from a binary encoded frequency control word, where the frequency control word may comprise hermometer coded signals and a pulse modulated dither signal, and may select a frequency control word signal line over which to transmit the pulse modulated dither signal and may transmit the thermometer coded signals over another of frequency control word signal lines. A digitally controlled oscillator may be configured to receive a frequency control word and generate an output clock signal at a frequency determined using at least the frequency control word.
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62.发明授权公开(公告)号：US09762250B2
公开(公告)日：2017-09-12
申请号：US14448458
申请日：2014-07-31
发明人： Michael H. Perrott
IPC分类号： H03L7/06 , H03L7/08 , H03L7/093 , H03M1/08 , H03M1/66 , G04F10/00 , H03L7/099 , H03M3/00 , H03L7/085 , H02M3/07 , H03M7/30
CPC分类号： H03L7/0802 , G04F10/005 , H02M3/07 , H03L7/085 , H03L7/093 , H03L7/0995 , H03M1/0836 , H03M1/0854 , H03M1/66 , H03M3/358 , H03M3/368 , H03M7/3004
摘要： A phase-locked loop (PLL) includes a spur cancellation circuit that receives a residue signal indicative of a first frequency and receives a residual phase error signal and generates a spur cancellation signal. A summing circuit combines the spur cancellation signal and a first phase error signal corresponding to a phase difference between a reference signal and a feedback signal in the PLL and generates a second phase error signal with a reduced spurious tone at the first frequency.
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公开(公告)号：US09762120B2
公开(公告)日：2017-09-12
申请号：US15174050
申请日：2016-06-06
发明人： Peter Vlasenko , Huy Tuong Mai
摘要： A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.
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64.发明授权公开(公告)号：US09735793B2
公开(公告)日：2017-08-15
申请号：US14962696
申请日：2015-12-08
CPC分类号： H03L7/24 , G06F1/08 , G06F1/10 , H01L23/5225 , H03K5/15013
摘要： A low power clock distribution circuit system (200) includes a clock generator (201) for generating a high frequency clock signal that is supplied to a clock interconnect running to multiple lanes of an integrated circuit, each lane including a passive clock repeater circuit (e.g., 203) having a differential-mode RLC network (e.g., 301) that is shielded by an active guard ring structure (e.g., 511) and that is coupled to receive first and second input clock signals (Vip, Vin) to provide clock signal gain boosting at a predetermined frequency range and clock signal attenuation out of the operating frequency range, thereby generating the first and second output clock signals (Vop, Von) that are provided to a clocked circuit (e.g., 211).
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65.发明授权公开(公告)号：US09735792B2
公开(公告)日：2017-08-15
申请号：US14651571
申请日：2014-01-03
申请人： Rambus Inc.
发明人： Jared L. Zerbe , Masum Hossain
CPC分类号： H03L7/24 , H03K3/0307 , H03K3/0315 , H03L1/00 , H03L7/06
摘要： Embodiments of an integrated circuit (IC) comprising circuitry to determine settings for an injection-locked oscillator (ILO) are described. In some embodiments, an injection signal is generated based on a first clock edge of a reference clock signal, and is injected into an ILO. Next, one or more output signals of the ILO are sampled based on a second clock edge of the reference clock signal, and settings for the ILO are determined based on the samples. In some embodiments, a sequence of two or more time-to-digital (TDC) codes is generated based on a reference clock signal and a free-running ILO. In some embodiments, the TDC circuitry that is already present in a delay-locked loop is reused for determining the sequence of two or more TDC codes. The ILO settings can then be determined based on the sequence of two or more TDC codes.
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公开(公告)号：US09735791B2
公开(公告)日：2017-08-15
申请号：US15130802
申请日：2016-04-15
申请人： Rambus Inc.
CPC分类号： H03L7/16 , H03J2200/10 , H03K3/0315 , H03K5/00006 , H03K5/13 , H03K5/14 , H03L7/06 , H03L7/0995 , H03L7/24
摘要： In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.
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公开(公告)号：US09729157B2
公开(公告)日：2017-08-08
申请号：US14622706
申请日：2015-02-13
发明人： Wim F. Cops
CPC分类号： H03L7/0814 , H03K5/06 , H03L7/0816
摘要： A variable phase generator is disclosed that includes a delay line with an input, and output, and a delay lone control signal input. A signal on the delay line output has a phase offset relative to the delay line input signal such that the phase offset is controlled by a digital offset signal. A phase detector process the input signal and the output signal to generate a phase detector output signal. A charge pump, responsive to the phase detector output signal, generates a charge pump output. A digital to analog converter receives and converts the digital offset signal to an analog offset signal. A control node is connected to the delay line control input, the charge pump, and the digital to analog converter, and is configured to receive and combine the charge pump output and the analog offset signal to create the delay line control signal.
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公开(公告)号：US09705516B1
公开(公告)日：2017-07-11
申请号：US15224296
申请日：2016-07-29
CPC分类号： H03L7/0995 , H03B5/1212 , H03B5/1228 , H03B5/1243 , H03L7/0998
摘要： A reconfigurable phase-locked loop integrated circuit is disclosed which is coupleable to an inductor, and may include: a memory storing a plurality of configuration parameters; a plurality of capacitive tuning circuits coupleable to the inductor to form an LC oscillator circuit to generate a first output signal having a first output frequency; a reconfigurable frequency and delay generator configurable as a ring oscillator or as a delay line circuit, and to generate a second output signal having a second output frequency; and a first digital controller to generate a first control signals to the reconfigurable frequency and delay generator to generate the second output signal having the second output frequency when the reconfigurable frequency and delay generator is configured as the ring oscillator; and to generate a second plurality of control signals to the plurality of capacitive tuning circuits to generate the first output signal having the first output frequency when the reconfigurable frequency and delay generator is configured as the delay line circuit.
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公开(公告)号：US09705512B1
公开(公告)日：2017-07-11
申请号：US15271182
申请日：2016-09-20
发明人： Chi-Kung Kuan , Yu Zhao , Chia-Liang Lin
CPC分类号： H03L7/0891 , H03L7/0898 , H03L7/093 , H03L7/0995 , H03L7/1974 , H03L7/1976
摘要： A circuit receives a reference clock and output an output clock in accordance with a clock multiplication factor, the circuit comprising: a digitally controlled timing adjustment circuit, a timing detection circuit, a loop filter, a controllable oscillator, a clock divider, a modulator, and a calibration circuit, wherein the modulator is configured to modulate a clock multiplication factor into a division factor and also calculate a pre-known noise caused by the modulation, and the digitally controlled timing adjustment circuit, the timing detection circuit, the loop filter, the controllable oscillator, and the clock divider form a feedback loop such that a frequency of the output clock is equal to a frequency of the reference clock multiplied by the clock multiplication, but a pre-known noise caused by the modulation is corrected by the digitally controlled timing adjustment circuit, which is calibrated by the calibration circuit in a closed-loop manner to minimize a correlation between the pre-known noise and an output of the timing detection circuit.
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公开(公告)号：US09660657B2
公开(公告)日：2017-05-23
申请号：US14804704
申请日：2015-07-21
发明人： Fumiyuki Adachi
CPC分类号： H03L7/189 , H03L7/0891 , H03L7/093 , H03L7/1976 , H03M7/3026 , H04B1/707
摘要： A spread spectrum clock generator includes: a phase comparing unit that receives a reference clock signal and a feedback clock signal, and generates a control voltage corresponding to a phase difference between the reference clock signal and the feedback clock signal; a voltage-controlled oscillator that oscillates at an oscillating frequency corresponding to the control voltage, and generates an output clock signal; a delta-sigma modulator that receives a waveform signal for controlling spreading of a spectrum of the output clock signal, and outputs bits larger than 1 bit based on the waveform signal; a control circuit that controls a multiplication number according to an output signal of the delta-signal modulator; and a divider that generates the feedback clock signal by dividing the output clock signal according to the multiplication number controlled by the control circuit, and supplies the feedback clock signal to the phase comparing unit.
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