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公开(公告)号：US10937491B2
公开(公告)日：2021-03-02
申请号：US16922883
申请日：2020-07-07
摘要： Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a certain number bits having a first logic state prior to storing the user data in memory cells. Subsequently, reading the encoded user data may be carried out by applying a read voltage to the memory cells while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. The auto-referenced read may identify a particular switching event that correlates to a median threshold voltage value of the subset of the memory cells. Then, the auto-referenced read may determine a reference voltage that takes into account a statistical property of threshold voltage distribution of the subset of the memory cells. The auto-referenced read may identify a time duration to maintain the read voltage based on determining the reference voltage. When the time duration expires, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.
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公开(公告)号：US10930343B2
公开(公告)日：2021-02-23
申请号：US16107063
申请日：2018-08-21
发明人： Amit S. Sharma , Suhas Kumar , Xia Sheng
摘要： A memristor device includes a first electrode, a second electrode, and a memristor layer disposed between the first electrode and the second electrode. The memristor layer is formed of a metal oxide. The memristor layer includes a plurality of regions that extend between the first electrode and the second electrode. The plurality of regions of the memristor layer are created with different concentrations of oxygen before electrical operation, and, during electrical operation, a voltage-conductance characteristic of the memristor device is controlled based on the different concentrations of oxygen of the plurality of regions. The controlling of the voltage-conductance characteristic includes increasing or decreasing the conductance of the memristor device toward a target conductance at a specific voltage.
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公开(公告)号：US20210036011A1
公开(公告)日：2021-02-04
申请号：US16844429
申请日：2020-04-09
发明人： Younghwan SON , Seogoo KANG , Jeehoon HAN
IPC分类号： H01L27/11582 , G11C8/14 , G11C7/18 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11565 , H01L29/423
摘要： A semiconductor device is disclosed. The semiconductor device includes a channel structure on a substrate and extending in a first direction perpendicular to a top surface of the substrate; a plurality of gate electrodes on the substrate and spaced apart from one another in the first direction on a sidewall of the channel structure; and a gate insulating layer between each of the plurality of gate electrodes and the channel structure, wherein the channel structure includes a body gate layer extending in the first direction; a charge storage structure surrounding a sidewall of the body gate layer; and a channel layer surrounding sidewall of the charge storage structure.
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公开(公告)号：US10910027B2
公开(公告)日：2021-02-02
申请号：US16382856
申请日：2019-04-12
发明人： Takamasa Suzuki
IPC分类号： G11C8/08 , G11C11/408 , G11C5/14 , G11C8/10 , G11C8/14
摘要： Apparatuses and methods for driving word driver lines in a gradual manner are disclosed herein. Word driver lines may be driven to intermediate potentials between high and low potentials. In some examples, the word driver lines may be driven in a step-wise manner. In some examples, the intermediate potential may be a bias voltage. The bias voltage may be provided by a bias voltage generator. One or more enable signals may be used to control the driving of the word driver line. In some examples, an address signal may be used to control the driving of the word driver line. Driving the word driver line in a gradual manner may cause a word line to discharge in a gradual manner in some examples.
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公开(公告)号：US10903419B2
公开(公告)日：2021-01-26
申请号：US16909663
申请日：2020-06-23
申请人： SK hynix Inc.
发明人： Hyuck Sang Yim , Myung Sun Song
摘要： A resistive memory device may include a plurality of MATs, row control blocks, a plurality of word lines, a plurality of bit lines and memory cells. Each of the row control blocks may be interposed between the MATs. Each of the row control blocks may include a control element. The word lines may be arranged spaced apart from each other by a substantially uniform gap on the MATs. The bit lines may overlap with the word lines. The memory cells may be located between the word lines and the bit lines. Each of the word lines may be electrically connected with the control element of each of the row control blocks via a connection path.
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公开(公告)号：US10903229B2
公开(公告)日：2021-01-26
申请号：US16162533
申请日：2018-10-17
发明人： Seok Cheon Baek , Sung Hun Lee
IPC分类号： H01L27/11582 , H01L27/11573 , H01L29/423 , G11C7/18 , G11C8/14 , H01L27/1157 , G11C5/02
摘要： A three-dimensional semiconductor memory device including a gate-stack structure on a base substrate, the gate-stack structure including gate electrodes stacked in a direction perpendicular to a surface of the base substrate and spaced apart from each other; a through region penetrating through the gate-stack structure and surrounded by the gate-stack structure; and first vertical channel structures and second vertical channel structures on both sides of the through region and penetrating through the gate-stack structure, wherein the through region is between the first vertical channel structures and the second vertical channel structures.
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公开(公告)号：US20210005629A1
公开(公告)日：2021-01-07
申请号：US17025479
申请日：2020-09-18
发明人： BONGSOON LIM , SANG-WAN NAM , SANG-WON PARK , SANG-WON SHIM , HONGSOO JEON , YONGHYUK CHOI
IPC分类号： H01L27/11582 , H01L27/11565 , H01L27/11556 , H01L27/11573 , H01L23/522 , G11C7/18 , H01L27/11519 , H01L27/11526 , G11C8/14
摘要： A three-dimensional semiconductor memory device may include a peripheral circuit structure including transistors on a first substrate, and a cell array structure on the peripheral circuit structure, the cell array structure including: a first stack structure block comprising first stack structures arranged side by side in a first direction on a second substrate, a second stack structure block comprising second stack structures arranged side by side in the first direction on the second substrate, a separation structure disposed on the second substrate between the first stack structure block and the second stack structure block and comprising first mold layers and second mold layers, and a contact plug penetrating the separation structure. The cell array structure may include a first metal pad and the peripheral circuit structure may include a second metal pad. The first metal pad may be in contact with the second metal pad.
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68.发明授权公开(公告)号：US10885956B2
公开(公告)日：2021-01-05
申请号：US16878481
申请日：2020-05-19
发明人： Chih Cheng Liu
IPC分类号： G11C7/12 , G11C8/14 , H01L27/108
摘要： A semiconductor layout structure for a dynamic random access memory (DRAM) array, comprising an isolation structure and a plurality of active areas situated in a semiconductor substrate, each of the active areas extending along a length-wise central axis. The isolation structure is situated among the active areas. The active areas are arranged in an array and comprise a plurality of first active areas and a plurality of second active areas. The first active areas are arranged along a first length-wise direction of the active areas. The second active areas are arranged along a second length-wise direction of the active areas. The first active areas are parallel and adjacent to the second active areas, and the first and second active areas are alternately distributed in a direction of word-lines. The first active area having a first width smaller than a second width of the second active area.
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公开(公告)号：US10861535B2
公开(公告)日：2020-12-08
申请号：US16159952
申请日：2018-10-15
申请人： SK hynix Inc.
发明人： Dong-Wook Kim
摘要： A memory system includes: a memory device including a three dimensional (3D) cell array, in which memory cells having the same height are coupled to a component word line by units of rows and component word lines having the same height are coupled to a group word line; and a controller suitable for controlling the memory device to perform a program operation with a program data into memory cells coupled to a data component word line selected from a plurality of component word line included in a single group word line and to perform a dummy program operation with dummy data into memory cells coupled to remaining dummy component word lines among the plurality of component word lines.
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公开(公告)号：US10859661B2
公开(公告)日：2020-12-08
申请号：US16924068
申请日：2020-07-08
发明人： Zengtao T. Liu
IPC分类号： G11C11/00 , G01R33/58 , G11C7/10 , H01L27/24 , G11C13/00 , G11C8/14 , H01L45/00 , G01R33/12 , G11C5/06 , G11C5/02 , G01R33/24
摘要： Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F2.
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