公开(公告)号：US20200273975A1

公开(公告)日：2020-08-27

申请号：US15930070

申请日：2020-05-12

申请人： ROHM CO., LTD.

发明人： Kenji YAMAMOTO ,  Tetsuya FUJIWARA ,  Minoru AKUTSU ,  Ken NAKAHARA ,  Norikazu ITO

IPC分类号： H01L29/778 ,  H01L29/423 ,  H01L21/76 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/28 ,  H01L29/417 ,  H01L21/265 ,  H01L21/311 ,  H01L29/51

摘要： A nitride semiconductor device includes an electron transit layer (103) that is formed of a nitride semiconductor, an electron supply layer (104) that is formed on the electron transit layer (103), that is formed of a nitride semiconductor whose composition is different from the electron transit layer (103) and that has a recess (109) which reaches the electron transit layer (103) from a surface, a thermal oxide film (111) that is formed on the surface of the electron transit layer (103) exposed within the recess (109), a gate insulating film (110) that is embedded within the recess (109) so as to be in contact with the thermal oxide film (111), a gate electrode (108) that is formed on the gate insulating film (110) and that is opposite to the electron transit layer (103) across the thermal oxide film (111) and the gate insulating film (110), and a source electrode (106) and a drain electrode (107) that are provided on the electron supply layer (104) at an interval such that the gate electrode (108) intervenes therebetween.

公开(公告)号：US10755976B2

公开(公告)日：2020-08-25

申请号：US16433627

申请日：2019-06-06

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kangguo Cheng ,  Chi-Chun Liu ,  Peng Xu

IPC分类号： H01L21/76 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H01L29/417

摘要： A method of forming source/drain contacts with reduced capacitance and resistance, including, forming a source/drain and a channel region on an active region of a substrate, forming a dielectric fill on the source/drain, forming a trench in the dielectric fill, forming a source/drain contact in the trench, forming an inner contact mask section on a portion of an exposed top surface of the source/drain contact, removing a portion of the source/drain contact to form a channel between a sidewall of the dielectric fill and a remaining portion of the source/drain contact, where a surface area of the remaining portion of the source/drain contact is greater than the surface area of the exposed top surface of the source/drain contact, and forming a source/drain electrode fill on the remaining portion of the source/drain contact.

公开(公告)号：US10741541B2

公开(公告)日：2020-08-11

申请号：US15284675

申请日：2016-10-04

申请人： Infineon Technologies Dresden GmbH & Co. KG

发明人： Joachim Weyers ,  Markus Schmitt ,  Armin Tilke ,  Stefan Tegen ,  Thomas Bertrams

IPC分类号： H01L27/02 ,  H01L21/762 ,  H01L21/02 ,  H01L29/66 ,  H01L29/861 ,  H01L21/76 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/739 ,  H01L29/78

摘要： A method of manufacturing a semiconductor device includes forming an amorphous silicon layer over a first isolation layer. The method further includes simultaneously forming a gate oxide layer of a transistor device and transforming the amorphous silicon layer into a polycrystalline silicon layer by a thermal oxidation process. Herein a cover oxide layer is formed on the polycrystalline silicon layer.

公开(公告)号：US10741487B2

公开(公告)日：2020-08-11

申请号：US15961642

申请日：2018-04-24

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Michael J. Seddon ,  Mark Griswold

IPC分类号： H01L21/76 ,  H01L23/522 ,  H01L23/34 ,  H01L21/786 ,  H01L21/02 ,  H01L23/12

摘要： Implementations of a silicon-on-insulator (SOI) die may include a silicon layer including a first side and a second side, and an insulative layer coupled directly to the second side of the silicon layer. The insulative layer may not be coupled to any other silicon layer.

公开(公告)号：US10734781B2

公开(公告)日：2020-08-04

申请号：US15775366

申请日：2016-11-16

申请人： President and Fellows of Harvard College

发明人： Ruffin E. Evans ,  Alp Sipahigil ,  Mikhail D. Lukin

IPC分类号： H01L21/76 ,  H01S3/16 ,  C09K11/59 ,  C09K11/66 ,  H01S3/063 ,  H01S3/0941 ,  G01N21/95

摘要： In an exemplary embodiment, a structure comprises a plurality of deterministically positioned optically active defects, wherein each of the plurality of deterministically positioned optically active defects has a linewidth within a factor of one hundred of a lifetime limited linewidth of optical transitions of the plurality of deterministically positioned optically active defects, and wherein the plurality of deterministically positioned optically active defects has an inhomogeneous distribution of wavelengths, wherein at least half of the plurality of deterministically positioned optically active defects have transition wavelengths within a less than 8 nm range. In a further exemplary embodiment, method of producing at least one optically active defect comprises deterministically implanting at least one ion in a structure using a focused ion beam; heating the structure in a vacuum at a first temperature to create at least one optically active defect; and heating the structure in the vacuum at a second temperature to remove a plurality of other defects in the structure, wherein the second temperature is higher than the first temperature.

公开(公告)号：US10727176B2

公开(公告)日：2020-07-28

申请号：US16287108

申请日：2019-02-27

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Daniel J. Buvid ,  Eric J. Campbell ,  Sarah K. Czaplewski ,  Christopher W. Steffen

IPC分类号： H05K1/00 ,  H05K1/11 ,  H05K3/10 ,  H05K3/18 ,  H01L21/20 ,  H01L21/76 ,  H01L21/768 ,  H01L23/52 ,  H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

摘要： A method of forming an interconnect that includes providing a sacrificial trace structure using an additive forming method. The sacrificial trace structure having a geometry for the interconnect. The method continuous with forming a continuous seed metal layer on the sacrificial trace structure; and removing the sacrificial trace structure, wherein the continuous seed metal layer remains. An interconnect metal layer may be formed on the continuous seed layer. A dielectric material may then be formed on the interconnect metal layer to encapsulate a majority of the interconnect metal layer, wherein ends of the interconnect metal layer are exposed through one surface of the dielectric material to provide an interconnect extending into a dielectric material.

公开(公告)号：US20200219870A1

公开(公告)日：2020-07-09

申请号：US16824779

申请日：2020-03-20

申请人： Vanguard International Semiconductor Corporation

发明人： Fu-Hsin CHEN ,  Shin-Cheng LIN ,  Yung-Hao LIN ,  Hsin-Chih LIN

IPC分类号： H01L27/06 ,  H01L29/778 ,  H01L21/8252 ,  H01L21/76 ,  H01L29/66 ,  H01L49/02 ,  H01L29/205 ,  H01L29/20 ,  H01L29/06

摘要： A semiconductor structure includes a substrate, a first III-V compound layer, a second III-V compound layer, a third III-V compound layer, and a fourth III-V compound layer. The top of the substrate includes a first region and a second region. The first III-V compound layer is in the first region. The second III-V compound layer is disposed over the first III-V compound layer. A first carrier channel is formed between the first III-V compound layer and the second III-V compound layer. The second III-V compound layer has a first thickness. The third III-V compound layer is in the second region. The fourth III-V compound layer is disposed over the third III-V compound layer. A second carrier channel is formed between the fourth III-V compound layer and the third III-V compound layer. The fourth III-V compound layer has a second thickness less than the first thickness.

公开(公告)号：US10700087B2

公开(公告)日：2020-06-30

申请号：US16151467

申请日：2018-10-04

申请人： Applied Materials, Inc.

发明人： Xinhai Han ,  Deenesh Padhi ,  Er-Xuan Ping ,  Srinivas Guggilla

IPC分类号： H01L21/76 ,  H01L27/11582 ,  H01L21/311 ,  H01L21/02 ,  H01L27/1157

摘要： Embodiments described herein relate to methods and materials for fabricating semiconductor devices, such as memory devices and the like. In one embodiment, a memory layer stack includes materials having differing etch rates in which one material is selectively removed to form an airgap in the device structure. In another embodiment, silicon containing materials of a memory layer stack are doped or fabricated as a silicide material. In another embodiment, a silicon nitride material is utilized as an interfacial layer between oxide containing and silicon containing layers of a memory layer stack.

公开(公告)号：US10685872B2

公开(公告)日：2020-06-16

申请号：US15992339

申请日：2018-05-30

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Peng Xu ,  Ekmini A. De Silva ,  Ruilong Xie

IPC分类号： H01L23/52 ,  H01L29/41 ,  H01L21/28 ,  H01L21/76 ,  H01L21/768 ,  H01L23/522 ,  H01L29/417 ,  H01L21/285 ,  H01L21/311

摘要： A semiconductor device is formed where a conductive extension (e.g., a TS) electrically couples with a first structure (e.g., an S/D) of the semiconductor device, a dielectric is deposited at least on a surface of a second structure (e.g., a gate), where the surface is substantially parallel to a plane of fabrication of the semiconductor device. An insulator cap surrounds an exposed portion of the extension. An opening is formed in the insulator cap, and a first contact (e.g., a CA) is formed through the opening to electrically couple with the first structure. A second contact (e.g., a CB) is formed through an opening in the dielectric at a first portion of the surface and electrically couples with the second structure. The dielectric continues to cover a second portion of the surface, and a portion of the insulator cap is interposed between the first contact and the second contact.

公开(公告)号：US10672657B2

公开(公告)日：2020-06-02

申请号：US15906366

申请日：2018-02-27

申请人： Micron Technology, Inc.

发明人： Matthew Park ,  Adam L. Olson ,  Jixin Yu

IPC分类号： H01L21/76 ,  H01L23/52 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/11548

摘要： A method of forming a semiconductor device assembly comprises forming tiers comprising conductive structures and insulating structures in a stacked arrangement over a substrate. Portions of the tiers are selectively removed to form a stair step structure comprising a selected number of steps exhibiting different widths corresponding to variances in projected error associated with forming the steps. Contact structures are formed on the steps of the stair step structure. Semiconductor device structures and semiconductor devices are also described.