公开(公告)号：US20150126141A1

公开(公告)日：2015-05-07

申请号：US14072898

申请日：2013-11-06

Applicant: STMicroelectronics International N.V.

Inventor： Patrik Arno

IPC: H04B1/04

CPC classification number: H04B1/0475 ,  H03F1/0238 ,  H03F1/3241 ,  H03F1/3247 ,  H03F1/3258 ,  H03F3/19 ,  H03F3/24 ,  H03F2200/102 ,  H03F2200/336 ,  H03F2200/504 ,  H03F2201/3212 ,  H03F2201/3233 ,  H04B2001/0425

Abstract: The output of a Radio Frequency (RF) Power Amplifier (PA) is sampled and down-converted, and the amplitude envelope of the baseband feedback signal is extracted. This is compared to the envelope of a transmission signal, and the envelope tracking modulation of the RF PA supply voltage VCC is adaptively pre-distorted to achieve a constant ISO-Gain (and phase) in the RF PA. In particular, a nonlinear function is interpolated from a finite number gain values calculated from the feedback and transmission signals. This nonlinear function is then used to pre-distort the transmission signal envelope, resulting in a constant gain at the RF PA over a wide range of supply voltage VCC values. Since the gains are calculated from a feedback signal, the pre-distortion may be recalculated at event triggers, such as an RF frequency change. Furthermore, the method improves nonlinearity in the entire transmitter chain, not just the RF PA.

Abstract translation: 对射频（RF）功率放大器（PA）的输出进行采样和下变频，并提取基带反馈信号的幅度包络。 将其与传输信号的包络进行比较，并且RF PA电源电压VCC的包络跟踪调制被自适应地预失真以在RF PA中实现恒定的ISO增益（和相位）。 特别地，从反馈和传输信号计算的有限数量的增益值内插非线性函数。 然后使用这种非线性函数对传输信号包络进行预失真，从而在宽范围的电源电压VCC值下在RF PA上产生恒定的增益。 由于根据反馈信号计算增益，所以可以在诸如RF频率变化的事件触发时重新计算预失真。 此外，该方法改善了整个发射机链中的非线性，而不仅仅是RF PA。

公开(公告)号：US09018046B2

公开(公告)日：2015-04-28

申请号：US13841099

申请日：2013-03-15

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l

Inventor： Joshipura Jwalant ,  Nitin Bansal ,  Amit Katyal ,  Massimiliano Picca

IPC: H01L21/82 ,  H05K3/30 ,  G06F17/50

CPC classification number: H05K3/30 ,  G06F17/5063 ,  Y10T29/49002 ,  Y10T29/4913 ,  Y10T29/49169

Abstract: An area efficient distributed device for integrated voltage regulators comprising at least one filler cell coupled between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size portion of said device is coupled to said I/O rails for distributing portions of said device on the periphery of said chip. The device is coupled as small size portion on the lower portion of said second filler cell for distributing said device on the periphery of said chip and providing maximal area utilization.

Abstract translation: 一种用于集成电压调节器的区域有效的分布式装置，其包括耦合在芯片的I / O轨上的一对PADS与至少一个具有所述装置的小尺寸部分的附加填充单元之间的填充单元耦合到所述I / O 用于在所述芯片的周围分配所述设备的部分的轨道。 该装置作为小尺寸部分耦合在所述第二填充单元的下部，用于将所述装置分布在所述芯片的外围并提供最大的面积利用率。

公开(公告)号：US09000964B2

公开(公告)日：2015-04-07

申请号：US14294300

申请日：2014-06-03

Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

Inventor： Stéphane Le Tual ,  Pratap Narayan Singh

IPC: H03M1/00 ,  H03M1/08 ,  H03K3/013 ,  G11C27/02 ,  H03K19/0185

CPC classification number: H03M1/08 ,  G11C27/024 ,  G11C27/026 ,  H03K3/013 ,  H03K19/018528

Abstract: The invention concerns a circuit comprising: a first transistor (202) having a first main current node coupled to a first voltage signal (CNVDD), a control node coupled to a second voltage signal (CPVDD) and a second main current node coupled to an output node (206) of the circuit; a second transistor (204) having a first main current node coupled to a third voltage signal (CNGND), a control node coupled to a fourth voltage signal (CPGND) and a second main current node coupled to said output node of the circuit; and circuitry (210, 212) adapted to generate said first, second, third and fourth voltage signals based on a pair of differential input signals (CP, CN), wherein said first and second voltage signals are both referenced to a first supply voltage (VDD) and wherein said third and fourth voltage signals are both referenced to a second supply voltage (GND).

Abstract translation: 本发明涉及一种电路，包括：具有耦合到第一电压信号（CNVDD）的第一主电流节点的第一晶体管（202），耦合到第二电压信号（CPVDD）的控制节点和耦合到第一电流信号 输出节点（206）; 第二晶体管（204），其具有耦合到第三电压信号（CNGND）的第一主电流节点，耦合到第四电压信号（CPGND）的控制节点和耦合到所述电路的所述输出节点的第二主电流节点; 以及适于基于一对差分输入信号（CP，CN）产生所述第一，第二，第三和第四电压信号的电路（210,212），其中所述第一和第二电压信号都参考第一电源电压 VDD），并且其中所述第三和第四电压信号都参考第二电源电压（GND）。

公开(公告)号：US09000857B2

公开(公告)日：2015-04-07

申请号：US13919195

申请日：2013-06-17

Applicant: STMicroelectronics International N.V.

Inventor： Abhirup Lahiri ,  Nitin Gupta

IPC: H03L1/00 ,  G05F1/10 ,  H03K3/03 ,  H03L7/085 ,  H03L7/099

CPC classification number: H03L7/085 ,  H03L7/0995

Abstract: A circuit generates a compensation signal that can remove noise in a VCO introduced by a supply signal (i.e., supply-side noise). The circuit includes two transistors connected in series. A resistor is connected between the gate of the first transistor and the supply signal, and a capacitor is connected between the gate of the second transistor and the supply signal. The circuit is designed so that the transconductance of one transistor is greater than or equal to twice the transconductance of a second transistor. The compensation signal is supplied through a capacitor, which compensates for capacitors in a VCO, to an internal supply node of the VCO. At the internal supply node, the compensation signal removes (or greatly reduces) the noise introduced by the supply signal noise, resulting in a less-noisy output signal from the VCO.

Abstract translation: 电路产生可以去除由电源信号引入的VCO（即电源侧噪声）中的噪声的补偿信号。 该电路包括串联连接的两个晶体管。 电阻器连接在第一晶体管的栅极和电源信号之间，电容器连接在第二晶体管的栅极和电源信号之间。 该电路被设计成使得一个晶体管的跨导大于或等于第二晶体管的跨导的两倍。 补偿信号通过补偿VCO中的电容器的电容器提供给VCO的内部电源节点。 在内部电源节点，补偿信号消除（或大大降低）由电源信号噪声引入的噪声，导致VCO噪声较小的输出信号。

公开(公告)号：US20150082060A1

公开(公告)日：2015-03-19

申请号：US14486042

申请日：2014-09-15

Applicant: STMicroelectronics International N.V.

Inventor： Hakan Persson ,  Christophe Viroulaud

IPC: G06F1/32 ,  G06F1/08

CPC classification number: G06F1/3203 ,  G06F1/08 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/171

Abstract: A power consumption management system for a central processing unit may include a power consumption estimation block and an activity control block. The power consumption estimation block may be configured to estimate power consumption of the central processing unit based on information related to a status of the central processing unit. The activity control block may be configured to use the estimated power consumption to determine a control to be applied to the central processing unit for regulating a rate of change in power consumption of the central processing unit.

Abstract translation: 用于中央处理单元的功耗管理系统可以包括功耗估计块和活动控制块。 功耗估计块可以被配置为基于与中央处理单元的状态相关的信息来估计中央处理单元的功耗。 活动控制块可以被配置为使用估计的功率消耗来确定要应用于中央处理单元的控制以调节中央处理单元的功率消耗的变化率。

公开(公告)号：US20150081983A1

公开(公告)日：2015-03-19

申请号：US14486215

申请日：2014-09-15

Applicant: STMicroelectronics International N.V.

Inventor： Gilles Ries ,  Ennio Salemi ,  Sana Ben Alaya

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/1027 ,  G06F2212/602 ,  G06F2212/654

Abstract: A memory management system for managing a memory and includes a multi-stage memory management unit including control circuitry and cache memory. The cache memory may have a respective translation look-aside buffer for each stage of the multi-stage memory management unit. The control circuitry may be configured to generate a blank data request including a virtual address and information that specifies that data is not to be read from the memory, perform address translations based on the generated blank data request in multiple stages until a physical address is obtained, and discard the blank data request.

Abstract translation: 一种用于管理存储器并且包括包括控制电路和高速缓冲存储器的多级存储器管理单元的存储器管理系统。 高速缓存存储器可以具有用于多级存储器管理单元的每个级的相应的翻译后备缓冲器。 控制电路可以被配置为生成包括虚拟地址的空白数据请求和指定不从存储器读取数据的信息，基于生成的空白数据请求，以多级执行地址转换，直到获得物理地址 ，并丢弃空白数据请求。

公开(公告)号：US08981817B2

公开(公告)日：2015-03-17

申请号：US13926748

申请日：2013-06-25

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Vinod Kumar ,  Pradeep Kumar Badrathwal ,  Saiyid Mohammad Irshad Rizvi ,  Paras Garg ,  Kallol Chatterjee ,  Pierre Dautriche

IPC: H03K3/00

CPC classification number: H03K19/00384

Abstract: A circuit having a centralized PT compensation circuit to provide compensation signals to localized I/O blocks on the chip. Process variations and temperature variations tend to be approximately uniform across an integrated circuit chip. Thus, a single, centralized PT compensation circuit may be used instead of one PT compensation circuit per I/O section as with solutions of the past. Further, the PT compensation circuit may generate a digital code indicative of the effects of process and temperature. Further yet, each section of I/O block may have a local voltage compensation circuit to compensate the voltage variation of the I/O block. The voltage compensation circuit utilizes an independent reference voltage. The reference voltage is generated by the PT compensation circuit, which is placed centrally in the IC chip and hence any need to repeat the reference generation for each I/O block is eliminated.

Abstract translation: 具有集中PT补偿电路以向芯片上的局部I / O块提供补偿信号的电路。 整个集成电路芯片的工艺变化和温度变化趋向于大致均匀。 因此，与过去的解决方案一样，可以使用单个集中式PT补偿电路来代替每个I / O部分的一个PT补偿电路。 此外，PT补偿电路可以产生指示过程和温度的影响的数字代码。 此外，I / O块的每个部分可以具有用于补偿I / O块的电压变化的局部电压补偿电路。 电压补偿电路采用独立的参考电压。 参考电压由放置在IC芯片中央的PT补偿电路产生，因此不需要重复每个I / O块的参考生成。

公开(公告)号：US20150055805A1

公开(公告)日：2015-02-26

申请号：US14461780

申请日：2014-08-18

Applicant: STMicroelectronics International N.V.

Inventor： Laurent Chevalier

IPC: H02M3/07 ,  G06F3/16 ,  G05F3/02

CPC classification number: H02M3/07 ,  G05F3/02 ,  G06F3/165 ,  H02M2001/009 ,  H02M2003/071 ,  H02M2003/072

Abstract: A multi level charge pump circuit may be associated with at least two power supplies, and may provide at least four levels of positive and negative voltage. The multi level charge pump may include first and second fly capacitors, and first and second tank capacitors. A plurality of PMOS transistors and NMOS transistors may allow generation of two high voltage levels and two low voltage levels for the multi level charge pump, the low voltage levels being derived from a charging of the two fly capacitors in series. This multi level charge pump may be embodied in an audio device within a platform without a dedicated SMPS circuit.

Abstract translation: 多级电荷泵电路可以与至少两个电源相关联，并且可以提供至少四个正电压和负电压电平。 多级电荷泵可以包括第一和第二飞电电容器，以及第一和第二容性电容器。 多个PMOS晶体管和NMOS晶体管可以允许为多电平电荷泵产生两个高电压电平和两个低电压电平，低电压电平是从两个串联的两个电容器的充电得到的。 该多电平电荷泵可以体现在平台内的音频装置中，而不需要专用的SMPS电路。

公开(公告)号：US20150055400A1

公开(公告)日：2015-02-26

申请号：US14532174

申请日：2014-11-04

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： NISHU KOHLI ,  MUDIT BHARGAVA ,  SHISHIR KUMAR

IPC: G11C7/22 ,  G11C7/06

CPC classification number: G11C7/227 ,  G11C7/06 ,  G11C7/08 ,  G11C7/22 ,  G11C7/222 ,  G11C29/12015 ,  G11C29/14 ,  G11C29/50 ,  G11C29/50012

Abstract: Delays are introduced in self-timed memories by introducing a capacitance on the path of a signal to be delayed. The capacitances are realized by using idle-lying metal layers in the circuitry. The signal to be delayed is connected to the idle-lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal, which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since idle-lying metal capacitances are utilized, the circuitry can be implemented using a minimum amount of additional hardware. Also, the delay provided by the circuitry is a function of memory cell SPICE characteristics and core parasitic capacitances.

Abstract translation: 通过在要延迟的信号的路径上引入电容，在自定时存储器中引入延迟。 电容通过在电路中使用空闲的金属层来实现。 要延迟的信号通过可编程开关连接到空载电容。 引入的延迟量取决于在信号路径中引入的电容，这又取决于开关的状态。 开关的状态由延迟引入电路外部提供的延迟代码来控制。 由于利用空闲位置的金属电容，所以可以使用最小量的附加硬件实现电路。 此外，由电路提供的延迟是存储器单元SPICE特性和内核寄生电容的函数。

公开(公告)号：US20150002916A1

公开(公告)日：2015-01-01

申请号：US14479615

申请日：2014-09-08

Applicant: STMicroelectronics International N.V.

Inventor： Sason Sourani ,  Moshe Medina

IPC: H02N1/00 ,  B81B7/00 ,  G02B7/182

CPC classification number: H02N1/006 ,  B81B3/0043 ,  B81B7/00 ,  B81B7/008 ,  B81B2201/033 ,  B81B2201/034 ,  B81B2201/042 ,  B81B2203/0109 ,  B81B2203/0181 ,  B81B2203/058 ,  G02B7/1821 ,  G02B26/0841 ,  H02N1/008

Abstract: A Micro Electro Mechanical Systems (MEMS) device includes a rotor having first rotor teeth and second rotor teeth formed in at least two layers of silicon-on-insulator (SOI) substrate. Each rotor tooth belonging to the first rotor teeth is formed in a first layer and each rotor tooth belonging of the second rotor teeth is formed in a second layer. A stator includes first stator teeth and second stator teeth formed in at least two layers of SOI substrate. Each stator tooth belonging to the first stator teeth is formed in a first layer and each stator tooth belonging to the second stator teeth is formed in a second layer.

Abstract translation: 微机电系统（MEMS）装置包括具有形成在至少两层绝缘体上硅（SOI）衬底上的第一转子齿和第二转子齿的转子。 属于第一转子齿的每个转子齿形成在第一层中，并且属于第二转子齿的每个转子齿形成在第二层中。 定子包括形成在至少两层SOI衬底中的第一定子齿和第二定子齿。 属于第一定子齿的每个定子齿形成在第一层中，并且属于第二定子齿的每个定子齿形成在第二层中。