公开(公告)号：US20220238516A1

公开(公告)日：2022-07-28

申请号：US17463252

申请日：2021-08-31

Applicant: Yanbiao Pan ,  Robert Martin Higgins ,  Pushpa Mahalingam ,  Bhaskar Srinivasan

Inventor： Yanbiao Pan ,  Robert Martin Higgins ,  Pushpa Mahalingam ,  Bhaskar Srinivasan

IPC: H01L27/08 ,  H01L49/02 ,  H01L21/02

Abstract: Described examples include a resistor having a substrate having a non-conductive surface and a patterned polysilicon layer on the non-conductive surface, the patterned polysilicon layer including polycrystalline silicon wherein at least 90% of the grains in the polycrystalline silicon are 30 nm or smaller. The resistor also has a first terminal in conductive contact with the patterned polysilicon layer and a second terminal in conductive contact with the polysilicon layer and spaced from the first contact.

公开(公告)号：US08637113B2

公开(公告)日：2014-01-28

申请号：US13354163

申请日：2012-01-19

Applicant: Gurtej Sandhu ,  John Smythe ,  Bhaskar Srinivasan

Inventor： Gurtej Sandhu ,  John Smythe ,  Bhaskar Srinivasan

IPC: C23C18/00 ,  C23C20/00 ,  C23C28/00 ,  C23C30/00 ,  H01C17/06

CPC classification number: H01L27/101 ,  H01L21/0271 ,  Y10S438/947

Abstract: A method of forming a non-volatile resistive oxide memory array includes forming a plurality of one of conductive word lines or conductive bit lines over a substrate. Metal oxide-comprising material is formed over the plurality of said one of the word lines or bit lines. A series of elongated trenches is provided over the plurality of said one of the word lines or bit lines. A plurality of self-assembled block copolymer lines is formed within individual of the trenches in registered alignment with and between the trench sidewalls. A plurality of the other of conductive word lines or conductive bit lines is provided from said plurality of self-assembled block copolymer lines to form individually programmable junctions comprising said metal oxide-comprising material where the word lines and bit lines cross one another.

Abstract translation: 形成非易失性电阻氧化物存储器阵列的方法包括在衬底上形成多个导电字线或导电位线。 含金属氧化物的材料形成在多条所述一条字线或位线中。 在多个所述一条字线或位线之间提供一系列细长的沟槽。 多个自组装嵌段共聚物线形成在沟槽中的各个内，与沟槽侧壁之间对准并且在沟槽侧壁之间形成。 从所述多个自组装嵌段共聚物线路提供多个导电字线或导电位线，以形成包含所述金属氧化物的材料的单独可编程的结，其中字线和位线彼此交叉。

公开(公告)号：US08634224B2

公开(公告)日：2014-01-21

申请号：US12855624

申请日：2010-08-12

Applicant: Bhaskar Srinivasan ,  Gurtej S. Sandhu

Inventor： Bhaskar Srinivasan ,  Gurtej S. Sandhu

IPC: G11C11/00

CPC classification number: G11C13/0002 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/12 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/52 ,  G11C2213/56 ,  G11C2213/77 ,  H01L27/101 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1206

Abstract: In one aspect, a method of operating a memory cell includes using different electrodes to change a programmed state of the memory cell than are used to read the programmed state of the memory cell. In one aspect, a memory cell includes first and second opposing electrodes having material received there-between. The material has first and second lateral regions of different composition relative one another. One of the first and second lateral regions is received along one of two laterally opposing edges of the material. Another of the first and second lateral regions is received along the other of said two laterally opposing edges of the material. At least one of the first and second lateral regions is capable of being repeatedly programmed to at least two different resistance states. Other aspects and implementations are disclosed.

Abstract translation: 一方面，操作存储单元的方法包括使用不同的电极来改变存储器单元的编程状态，而不是用于读取存储单元的编程状态。 在一个方面，存储单元包括第一和第二相对电极，其间具有接收在其间的材料。 该材料具有彼此不同组成的第一和第二横向区域。 第一和第二横向区域中的一个沿着材料的两个横向相对的边缘中的一个被接收。 第一和第二横向区域中的另一个沿着材料的所述两个横向相对的边缘中的另一个被容纳。 第一和第二横向区域中的至少一个能够被重复编程至至少两个不同的阻力状态。 公开了其他方面和实现。

公开(公告)号：US08526415B2

公开(公告)日：2013-09-03

申请号：US11240401

申请日：2005-09-30

Applicant: Arati Manjeshwar ,  Lakshmi Venkatraman ,  Bhaskar Srinivasan

Inventor： Arati Manjeshwar ,  Lakshmi Venkatraman ,  Bhaskar Srinivasan

IPC: H04J3/00

CPC classification number: H04L12/1868 ,  H04L12/1881

Abstract: A method and system to acknowledge a multicast message includes informing each node in a network about each multicast group to which it belongs, a relative position in each multicast group to which it belongs, and a group size of each multicast group to which it belongs, transmitting the multicast message, and transmitting, by each node in the multicast group, an acknowledgment in an assigned slot, which is determined by the relative position.

Abstract translation: 确认组播消息的方法和系统包括：通知网络中每个组播组所属的每个组播组的每个节点，所属节点的每个组播组中的相对位置以及它所属的每个组播组的组大小， 发送多播消息，并且由多播组中的每个节点发送由相对位置确定的分配时隙中的确认。

公开(公告)号：US20130187117A1

公开(公告)日：2013-07-25

申请号：US13355382

申请日：2012-01-20

Applicant: Gurtej S. Sandhu ,  Bhaskar Srinivasan

Inventor： Gurtej S. Sandhu ,  Bhaskar Srinivasan

IPC: H01L45/00 ,  H01L21/8239

CPC classification number: H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1608

Abstract: Some embodiments include memory cells which contain, in order; a first electrode material, a first metal oxide material, a second metal oxide material, and a second electrode material. The first metal oxide material has at least two regions which differ in oxygen concentration relative to one another. One of the regions is a first region and another is a second region. The first region is closer to the first electrode material than the second region, and has a greater oxygen concentration than the second region. The second metal oxide material includes a different metal than the first metal oxide material. Some embodiments include methods of forming memory cells in which oxygen is substantially irreversibly transferred from a region of a metal oxide material to an oxygen-sink material. The oxygen transfer creates a difference in oxygen concentration within one region of the metal oxide material relative to another.

公开(公告)号：US08476140B2

公开(公告)日：2013-07-02

申请号：US13352833

申请日：2012-01-18

Applicant: Gurtej Sandhu ,  Bhaskar Srinivasan

Inventor： Gurtej Sandhu ,  Bhaskar Srinivasan

IPC: H01L21/8222 ,  H01L21/20

CPC classification number: H01L29/24 ,  H01L27/24 ,  H01L45/00

Abstract: A diode and memory device including the diode, where the diode includes a conductive portion and another portion formed of a first material that has characteristics allowing a first decrease in a resistivity of the material upon application of a voltage to the material, thereby allowing current to flow there through, and has further characteristics allowing a second decrease in the resistivity of the first material in response to an increase in temperature of the first material.

Abstract translation: 包括二极管的二极管和存储器件，其中二极管包括导电部分和由第一材料形成的另一部分，该第一材料具有允许在向材料施加电压时第一次降低材料的电阻率的特性，从而允许电流 流过其中，并且具有允许第一材料的电阻率响应于第一材料的温度升高而第二次降低的特征。

公开(公告)号：US08399952B2

公开(公告)日：2013-03-19

申请号：US13103162

申请日：2011-05-09

Applicant: Bhaskar Srinivasan ,  Vassil Antonov ,  John Smythe

Inventor： Bhaskar Srinivasan ,  Vassil Antonov ,  John Smythe

IPC: H01L21/00

CPC classification number: H01L28/75 ,  C23C16/404 ,  C23C16/409 ,  C23C16/45527 ,  C23C16/45529 ,  C23C16/45531 ,  C23C16/56 ,  H01G4/33 ,  H01L21/02197 ,  H01L21/022 ,  H01L21/0228 ,  H01L28/56 ,  H01L28/65

Abstract: Strontium ruthenium oxide provides an effective interface between a ruthenium conductor and a strontium titanium oxide dielectric. Formation of the strontium ruthenium oxide includes the use of atomic layer deposition to form strontium oxide and subsequent annealing of the strontium oxide to form the strontium ruthenium oxide. A first atomic layer deposition of strontium oxide is preformed using water as an oxygen source, followed by a subsequent atomic layer deposition of strontium oxide using ozone as an oxygen source.

Abstract translation: 钌氧化钌提供钌导体和锶钛氧化物电介质之间的有效界面。 锶氧化钌的形成包括使用原子层沉积形成氧化锶，随后退火氧化锶以形成氧化锶锶。 使用水作为氧源来进行氧化锶的第一原子层沉积，然后使用臭氧作为氧源，随后用氧化锶沉积氧化锶。

公开(公告)号：US08343828B2

公开(公告)日：2013-01-01

申请号：US13305072

申请日：2011-11-28

Applicant: Gurtej Sandhu ,  Bhaskar Srinivasan

Inventor： Gurtej Sandhu ,  Bhaskar Srinivasan

IPC: H01L21/8234

CPC classification number: H01L21/04 ,  H01L27/1021 ,  H01L27/2418 ,  H01L29/1606 ,  H01L45/00

Abstract: Some embodiments include methods of forming diodes. A stack may be formed over a first conductive material. The stack may include, in ascending order, a sacrificial material, at least one dielectric material, and a second conductive material. Spacers may be formed along opposing sidewalls of the stack, and then an entirety of the sacrificial material may be removed to leave a gap between the first conductive material and the at least one dielectric material. In some embodiments of forming diodes, a layer may be formed over a first conductive material, with the layer containing supports interspersed in sacrificial material. At least one dielectric material may be formed over the layer, and a second conductive material may be formed over the at least one dielectric material. An entirety of the sacrificial material may then be removed.

公开(公告)号：US08236372B2

公开(公告)日：2012-08-07

申请号：US12483455

申请日：2009-06-12

Applicant: Rishikesh Krishnan ,  John Smythe ,  Vishwanath Bhat ,  Noel Rocklein ,  Bhaskar Srinivasan ,  Jeff Hall ,  Chris Carlson

Inventor： Rishikesh Krishnan ,  John Smythe ,  Vishwanath Bhat ,  Noel Rocklein ,  Bhaskar Srinivasan ,  Jeff Hall ,  Chris Carlson

IPC: B05D5/12

CPC classification number: H01G4/12 ,  H01G4/1272 ,  H01G4/33 ,  H01L28/40

Abstract: Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal capacitor electrode. A capacitor dielectric region is received between the inner and the outer conductive metal capacitor electrodes and has a thickness no greater than 150 Angstroms. Various combinations of materials of thicknesses and relationships relative one another are disclosed which enables and results in the dielectric region having a dielectric constant k of at least 35 yet leakage current no greater than 1×10−7 amps/cm2 at from −1.1V to +1.1V.

Abstract translation: 公开了形成电容器的电容器和方法，其包括内部导电金属电容器电极和外部导电金属电容器电极。 电容器电介质区域被容纳在内导电金属电容电极和外导电金属电容器电极之间，并且具有不大于150埃的厚度。 公开了厚度和关系的材料的各种组合，其相互之间可以实现和导致电介质区域的介电常数k至少为35，而在-1.1V至-1.0V的范围内漏电流不大于1×10-7Aps / cm 2 + 1.1V。

公开(公告)号：US08199556B2

公开(公告)日：2012-06-12

申请号：US12564265

申请日：2009-09-22

Applicant: Bhaskar Srinivasan ,  Gurtej S. Sandhu

Inventor： Bhaskar Srinivasan ,  Gurtej S. Sandhu

IPC: G11C11/00

CPC classification number: G11C13/004 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0061 ,  G11C2013/0052 ,  G11C2213/72

Abstract: Some embodiments include methods of reading memory cells. The memory cells have a write operation that occurs only if a voltage of sufficient absolute value is applied for a sufficient duration of time; and the reading is conducted with a pulse that is of too short of a time duration to be sufficient for the write operation. In some embodiments, the pulse utilized for the reading may have an absolute value of voltage that is greater than or equal to the voltage utilized for the write operation. In some embodiments, the memory cells may comprise non-ohmic devices; such as memristors and diodes.

Abstract translation: 一些实施例包括读取存储器单元的方法。 存储器单元具有写入操作，只有当足够的绝对值的电压施加足够的持续时间时才发生; 并且读取是用太短的持续时间的脉冲来进行的，以足以用于写入操作。 在一些实施例中，用于读取的脉冲可以具有大于或等于用于写入操作的电压的绝对值。 在一些实施例中，存储器单元可以包括非欧姆器件; 如忆阻器和二极管。