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公开(公告)号：US09385733B2
公开(公告)日：2016-07-05
申请号：US14527779
申请日：2014-10-30
Applicant: Faraday Technology Corp.
Inventor： Chia-Liang Lai , Song-Rong Han , Jung-Yu Chang , Wei-Ming Lin
CPC classification number: H03L7/1976 , H03K21/023 , H03K23/68 , H03L7/1974
Abstract: A clock generating apparatus and a fractional frequency divider thereof are provided. The fractional frequency divider includes a frequency divider (FD), a plurality of samplers, a selector and a control circuit. An input terminal of the FD is coupled to an output terminal of a multi-phase-frequency generating circuit. Input terminals of the samplers are coupled to an output terminal of the FD. Trigger terminals of the samplers receive the sampling clock signals. The input terminals of the selector are coupled to output terminals of the samplers. An output terminal of the selector is coupled to a feedback terminal of the multi-phase-frequency generating circuit. The control circuit provides a fraction code to a control terminal of the selector, so as to control the selector for selectively coupling the output terminal of one of the samplers to the feedback terminal of the multi-phase-frequency generating circuit.
Abstract translation: 提供时钟发生装置及其分数分频器。 分数分频器包括分频器（FD），多个采样器，选择器和控制电路。 FD的输入端耦合到多相频率发生电路的输出端。 采样器的输入端耦合到FD的输出端。 采样器的触发端接收采样时钟信号。 选择器的输入端耦合到采样器的输出端。 选择器的输出端耦合到多相频率发生电路的反馈端。 控制电路向选择器的控制端提供分数代码，以便控制选择器选择性地将一个采样器的输出端耦合到多相频率发生电路的反馈端。
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公开(公告)号：US20250023559A1
公开(公告)日：2025-01-16
申请号：US18351513
申请日：2023-07-13
Applicant: Faraday Technology Corp.
Inventor： Vinod Kumar Jain , Mikhail Tamrazyan
Abstract: A conversion circuit includes a replica feedback loop circuit and a CML to CMOS converter. The replica feedback loop circuit of a conversion circuit includes a first inverter, a first-stage amplifier and a second-stage amplifier. An input terminal of the first inverter is shorted to an output terminal of the first inverter. The second-stage amplifier of the replica feedback loop circuit is a replica of a half of a differential amplifier of the CML to CMOS converter. The replica feedback loop circuit is configured to generate a bias voltage that is used to bias the differential amplifier of the CML to CMOS converter, such that a common mode (CM) voltage outputted by the differential amplifier is same as a switching threshold voltage of a second inverter of the CML to CMOS converter.
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73.发明授权公开(公告)号：US11935577B2
公开(公告)日：2024-03-19
申请号：US17667499
申请日：2022-02-08
Applicant: Faraday Technology Corp.
Inventor： Sridhar Cheruku , Sivaramakrishnan Subramanian , Hussainvali Shaik , Ko-Ching Chao
IPC: G11C7/22 , G11C7/10 , G11C11/4076 , G11C11/4096
CPC classification number: G11C11/4076 , G11C7/1093 , G11C7/222 , G11C11/4096 , G11C7/1087
Abstract: The present invention provides a physical layer and associated signal processing method for clock domain transfer of quarter-rate data. In the embodiments of the present invention, the quarter-rate data is processed by many sampling circuits by using a first clock signal, a second clock signal and a third clock signal, and phases of these clock signals are aligned by using a training mechanism to that the clock signals have better timing margins.
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公开(公告)号：US11831287B2
公开(公告)日：2023-11-28
申请号：US17531811
申请日：2021-11-22
Applicant: Faraday Technology Corp.
Inventor： Prateek Kumar Goyal , Raghu Nandan Chepuri , Vinod Kumar Jain
CPC classification number: H03G3/3084 , H03F3/45 , H03M1/12 , H04B10/6933 , H03F2200/375 , H03F2203/45212
Abstract: A method for removing offset in a receiver of an integrated circuit (IC) includes: determining digital codes of differential input voltages of an amplifier in a first receiving lane of the receiver; comparing the digital codes to a digital code corresponding to an optimum common mode voltage (VCM) of the receiver; according to the comparison, determining a bias code for adjusting both the differential input voltages to match the optimum VCM; and inputting the bias code to a bias circuit of the receiver. The first receiving lane of the receiver includes a plurality of amplifiers. The method steps are repeated for each amplifier of the plurality of amplifiers, and then repeated for all receiving lanes of the IC.
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公开(公告)号：US20230244190A1
公开(公告)日：2023-08-03
申请号：US17732432
申请日：2022-04-28
Applicant: Faraday Technology Corporation , Faraday Technology Corp.
Inventor： Ling Chen , Prateek Kumar GOYAL , Xiao-Dong Fei
IPC: G05B13/02
CPC classification number: G05B13/025 , G05B13/026
Abstract: A receiver device and an eye pattern-based control parameter adjustment method are provided. The receiver device includes a receiving circuit and a control circuit. The control circuit performs an iterative operation to determine an optimized control parameter, and updates current control parameters of the receiving circuit to the optimized control parameter after completing the iterative operation. The receiving circuit processes an input signal according to the current control parameters to generate recovered data. The iterative operation includes: updating the current control parameters of the receiving circuit to candidate control parameters; checking a size relationship between an optimized eye mask and a current eye pattern; and increasing the optimized eye mask according to the current eye pattern when the optimized eye mask does not conflict with the current eye pattern, and updating the optimized control parameters to the candidate control parameters corresponding to the new eye mask.
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Patent Agency Ranking
公开(公告)号：US20230231560A1
公开(公告)日：2023-07-20
申请号：US17974532
申请日：2022-10-27
Applicant: Faraday Technology Corp.
Inventor： Ko-Ching Chao , Chih-Hung Wu , Po-Wen Hsiao , Zhou-Lun Liou
IPC: H03L7/00 , H03K19/21 , H03K21/02 , G11C11/4076
CPC classification number: H03L7/00 , H03K19/21 , H03K21/023 , G11C11/4076
Abstract: A method for performing divided-clock phase synchronization in a multi-divided-clock system, an associated synchronization control circuit, an associated synchronization control sub-circuit and an associated electronic device are provided. The method may include: performing frequency division operations according to a source clock to generate a first divided clock and a second divided clock; performing phase relationship detection on the first divided clock according to the second divided clock to generate a phase relationship detection result signal; performing a logic operation on a first phase selection result output signal and the phase relationship detection result signal to generate a second phase selection result output signal; and outputting one of the second divided clock and an inverted signal of the second divided clock according to the second phase selection result output signal, for further use in a physical layer circuit.
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公开(公告)号：US11032055B1
公开(公告)日：2021-06-08
申请号：US17006904
申请日：2020-08-31
Applicant: Faraday Technology Corp.
Inventor： Yu-Hsin Tseng
Abstract: A clock data recovery circuit including a phase blender, a phase detector, a data sampling position detector and a data selector is provided. The phase blender generates a third clock signal and a fourth clock signal according to a first clock signal and a second clock signal. The phase detector samples a data signal according to the first and second clock signals to generate first sampled data, second sampled data and a phase state signal. The data sampling position detector samples the data signal according to the third and fourth clock signals to generate third sampled data, fourth sampled data and a control signal. The data selector generates output data according to the control signal and the phase state signal.
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公开(公告)号：US11005468B1
公开(公告)日：2021-05-11
申请号：US17016333
申请日：2020-09-09
Applicant: Faraday Technology Corp.
Inventor： Sivaramakrishnan Subramanian , Sridhar Cheruku , Sandeep Kumar Mohanta , Hussainvali Shaik
Abstract: A method for performing duty-cycle correction of an output clock in a Double Data Rate (DDR) system includes: setting a fixed delay of a rising-edge of the output clock as a parameter X which is equal to a digital Master Delay Locked Loop (MDLL) code of the DDR system multiplied by a percentage representing an estimated distortion of the duty-cycle of the output clock from a desired duty-cycle; shifting the rising-edge of the output clock by the fixed delay; and determining whether a duty cycle of the shifted output clock meets the desired duty-cycle. When a duty-cycle of the shifted output clock meets the desired duty-cycle, the fixed rising-edge delay is taken as a final delay code for the output clock; otherwise, a falling-edge of the output clock is shifted by an amount in a range between 0 and NX, wherein N is an integer.
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公开(公告)号：US20210066286A1
公开(公告)日：2021-03-04
申请号：US16745349
申请日：2020-01-17
Applicant: Faraday Technology Corp.
Inventor： Chia-Ku Tsai , Tsung-Hsiao Lin
IPC: H01L27/02 , H01L27/092 , H01L29/861
Abstract: The electrostatic discharge (ESD) protection apparatus includes a first well, a second well, a first doping region, and a second doping region. The first well is disposed in a substrate having a first conductivity type, wherein the first well has a second conductivity type and the substrate is electrically connected to a first pad. The second well is disposed in the first well, wherein the second well has the first conductivity type. The first doping region is disposed in the second well, wherein the first doping region has the second conductivity type, and the first doping region is electrically connected to a second pad. The second doping region is disposed in the second well, wherein the second doping region has the first conductivity type.
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公开(公告)号：US10812057B1
公开(公告)日：2020-10-20
申请号：US16726943
申请日：2019-12-26
Applicant: Faraday Technology Corp.
Inventor： Pei-Yuan Chou , Jinn-Shyan Wang , Chuen-Shiu Chen
Abstract: A time detection circuit and a time detection method are provided. The time detection circuit includes an input signal processor and a time signal amplifier. The input signal processor receives a first input signal and a second input signal, calculates a time difference value between the first input signal and the second input signal, adjusts the time difference value by comparing the time difference value with a set reference value, and provides the adjusted time difference value. The time signal amplifier receives the adjusted time difference value, and amplifies the adjusted time difference value to generate an amplified time signal. The time signal amplifier operates in a linear operation region between a first time value and a second time value, and the set reference value is set according to the first time value and the second time value.
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