公开(公告)号：US20240222356A1

公开(公告)日：2024-07-04

申请号：US18149279

申请日：2023-01-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： James P. Mazza ,  Jia Zeng ,  Xuelian Zhu ,  Navneet K. Jain ,  Mahbub Rashed ,  Jacob Mazza

IPC: H01L27/02

CPC classification number: H01L27/0207

Abstract: A multi-row standard cell and an integrated circuit (IC) structure using the standard cell are provided. The IC structure includes a plurality of cell rows extending in a first direction. At least two cell rows of the plurality of cell rows have different row heights. The IC structure includes a multi-row standard cell positioned in two or more cell rows having different row heights. At least one active region is shared by portions of the multi-row cell across the at least two cell rows. The IC structure may also include one or more asymmetric shared power rails disposed in an asymmetric manner across a row boundary between the at least two cell rows of different row heights. The multi-row standard cells and IC structures allow placement of multi-row cells for mixed track height arrangements in a manner not limited to multiples of row heights.

公开(公告)号：US12028053B2

公开(公告)日：2024-07-02

申请号：US17643567

申请日：2021-12-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： Steven M. Shank ,  Yves T. Ngu ,  Michael J. Zierak ,  Siva P. Adusumilli

IPC: H03K17/10 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/12 ,  H03K17/693

CPC classification number: H03K17/102 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/1203 ,  H03K17/693 ,  H03K2217/0018

Abstract: A structure includes a field effect transistor (FET) stack including a plurality of transistors over a buried insulator layer. A polysilicon isolation region is in a substrate below the FET stack and the buried insulator layer. A resistor network is in the polysilicon isolation region, the resistor network having a different resistivity than the polysilicon isolation region. The resistor network may include a resistive wire having a first width and a resistive pad within the resistive wire under each FET in the FET stack. Each resistive pad has a second width larger than the first width of the resistive wire. A length of the resistive wire is different aside each resistive pad to adjust a threshold voltage of an adjacent FET in the FET stack to a predetermined value to compensate for non-linear voltage distribution between an input and an output of the FET stack.

公开(公告)号：US12027226B2

公开(公告)日：2024-07-02

申请号：US17810018

申请日：2022-06-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Venkatesh P. Gopinath ,  Navneet K. Jain ,  Sven Beyer

IPC: G11C16/04 ,  G11C5/06 ,  G11C11/22 ,  G11C13/00

CPC classification number: G11C5/063 ,  G11C11/22 ,  G11C13/0028 ,  G11C13/0069

Abstract: The structure includes transistors in rows and columns and each having an electric field-based programmable threshold voltage at either a first threshold voltage (VT) or a second VT. The structure further includes first and second signal lines for the rows and columns, respectively. Each first signal line is connected to transistors in a row and each second signal line is connected to transistors in a column. When operated in a switch mode, the transistors may or may not become conductive depending upon their respective VTs. Conductive transistors form connected pairs of first and second signal lines and, thus, create signal paths. The structure can also include mode control circuitry to selectively operate the transistors in either a program mode to set a first VT or an erase mode to set a second VT and to concurrently operate the transistors in the switch mode.

公开(公告)号：US12005389B1

公开(公告)日：2024-06-11

申请号：US18479346

申请日：2023-10-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Justin Weinstein ,  Kimberly E. Konar

IPC: B01D53/04 ,  B01D53/40 ,  B01D53/82 ,  H01L21/67

CPC classification number: B01D53/0446 ,  B01D53/0423 ,  B01D53/40 ,  B01D53/82 ,  B01D2253/102 ,  B01D2258/0216 ,  B01D2259/4145 ,  H01L21/67017

Abstract: A system to abate an emission stream from a semiconductor manufacturing process is disclosed. The system includes a media canister to abate the emission stream in response to an abatement fault in an abatement apparatus. The media canister includes a reaction chamber configured to receive the emission stream in response to the abatement fault, and a dry media disposed within the reaction chamber to abate the emission stream. The dry media includes at least one reactive and/or absorbent material which catalyzes at least one chemical reaction to remove at least one pollutant from the emission stream and yield exhaust substantially free of the at least one pollutant.

公开(公告)号：US20240186441A1

公开(公告)日：2024-06-06

申请号：US18075908

申请日：2022-12-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Alexander M. DERRICKSON ,  Uppili S. RAGHUNATHAN ,  Vibhor JAIN ,  Yusheng BIAN ,  Judson R. HOLT

IPC: H01L31/11 ,  H01L31/0232 ,  H01L31/028 ,  H01L31/18

CPC classification number: H01L31/1105 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/1808

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to lateral phototransistors and methods of manufacture. The structure includes a lateral bipolar transistor; and a T-shaped photosensitive structure vertically above an intrinsic base of the lateral bipolar transistor.

公开(公告)号：US20240186384A1

公开(公告)日：2024-06-06

申请号：US18075930

申请日：2022-12-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Santosh SHARMA ,  Michael J. ZIERAK ,  Steven J. BENTLEY ,  Mark D. LEVY

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/402 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a high-electron-mobility transistor (HEMT) and methods of manufacture. The structure includes: a gate structure; a source contact and a drain contact adjacent to the gate structure; and a field plate electrically isolated from the gate structure and abutting the source contact and the drain contact.

公开(公告)号：US12001056B2

公开(公告)日：2024-06-04

申请号：US17834375

申请日：2022-06-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Bartlomiej Jan Pawlak ,  Michal Rakowski ,  Yusheng Bian

IPC: G02B6/293 ,  G02B6/42

CPC classification number: G02B6/2934 ,  G02B6/4215

Abstract: Structures including stacked photonics chips and methods of fabricating a structure including stacked photonics chips. The structure comprises a first chip including a first waveguide core, a ring resonator adjacent to a portion of the first waveguide core, and a first dielectric layer over the first waveguide core and the ring resonator. The first dielectric layer has a first surface. The structure further comprises a second chip including a second waveguide core and a second dielectric layer over the second waveguide core. The second dielectric layer has a second surface adjacent to the first surface of the first dielectric layer, and the second waveguide core is positioned adjacent to the ring resonator.

公开(公告)号：US20240177770A1

公开(公告)日：2024-05-30

申请号：US18058992

申请日：2022-11-28

Applicant: GlobalFoundries U.S. Inc.

Inventor： Bipul C. Paul ,  Chandrahasa Reddy Dinnipati

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2013/0042 ,  G11C2213/70

Abstract: A non-volatile memory (NVM) structure includes an array of memory cells. Within the array, data is stored in single cells or twin cells. The structure also includes switch circuits and sense amplifiers. Each switch circuit is connected between bitlines for a group of columns and a corresponding sense amplifier and establishes electrical connections to enable either single cell sensing or twin cell sensing. In single cell sensing, a data signal on a bitline connected to a memory cell is compared to a reference signal. In twin cell sensing, true and complement data signals on two bitlines connected to two memory cells are compared to each other. Since twin cell sensing compares true and complement data signals and does not require a reference signal, twin cell sensing is relatively accurate without the need for trim bits. Thus, the structure can store trim cells, accurately sense them, and subsequently use them.

公开(公告)号：US20240170531A1

公开(公告)日：2024-05-23

申请号：US18056289

申请日：2022-11-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sagar Premnath Karalkar ,  Jie Zeng ,  Souvick Mitra

IPC: H01L29/06 ,  H01L27/02

CPC classification number: H01L29/0623 ,  H01L27/0248

Abstract: The disclosure provides a structure with a buried doped region, and methods to form the same. A structure may include a semiconductor substrate including a first well. A first terminal includes a first doped region in the first well. A second terminal includes a second doped region in the first well. The first well horizontally separates the first doped region from the second doped region. A first buried doped region is in the first well. The first buried doped region overlaps with, and is underneath, the first doped region. The first well vertically separates the first doped region from the first buried doped region.

公开(公告)号：US20240159962A1

公开(公告)日：2024-05-16

申请号：US17985223

申请日：2022-11-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mark Levy ,  Siva P. Adusumilli ,  Yusheng Bian

IPC: G02B6/122 ,  G02B6/13

CPC classification number: G02B6/122 ,  G02B6/13 ,  G02B2006/12078

Abstract: Structures for a waveguide and methods of forming a waveguide. The structure comprises a substrate, a waveguide core comprising a compound semiconductor material, and a layer disposed on the substrate. The layer comprises the compound semiconductor material, and the layer includes a cavity positioned beneath the waveguide core.