公开(公告)号：US20100255651A1

公开(公告)日：2010-10-07

申请号：US12635013

申请日：2009-12-10

Applicant: Sang-yeol KANG ,  Jong-cheol LEE ,  Ki-vin LIM ,  Hoon-sang CHOI ,  Eun-ae CHUNG

Inventor： Sang-yeol KANG ,  Jong-cheol LEE ,  Ki-vin LIM ,  Hoon-sang CHOI ,  Eun-ae CHUNG

IPC: H01L21/02 ,  H01L21/31

CPC classification number: H01L28/40 ,  H01L27/10852

Abstract: A semiconductor device including a multilayer dielectric film and a method for fabricating the semiconductor device are disclosed. The multilayer dielectric film includes a type-one dielectric film having a tetragonal crystalline structure, wherein the type-one dielectric film comprises a first substance. The multilayer dielectric film also comprises a type-two dielectric film also having a tetragonal crystalline structure, wherein the type-two dielectric film comprises a second substance different from the first substance and a dielectric constant of the type-two dielectric film is greater than a dielectric constant of the type-one dielectric film.

Abstract translation: 公开了一种包括多层介质膜的半导体器件和用于制造半导体器件的方法。 所述多层电介质膜包括具有四方晶系结构的一型电介质膜，其中，所述一型电介质膜包含第一物质。 所述多层绝缘膜还包括也具有四方晶系结构的二型电介质膜，其中所述二型电介质膜包括与所述第一物质不同的第二物质，并且所述二型电介质膜的介电常数大于 介电常数介电常数为1。

公开(公告)号：US20100190320A1

公开(公告)日：2010-07-29

申请号：US12688044

申请日：2010-01-15

Applicant: Ki-chul Kim ,  Youn-soo Kim ,  Ki-vin Im ,  Cha-young Yoo ,  Jong-cheol Lee ,  Ki-yeon Park ,  Hoon-sang Choi ,  Se-hoon Oh

Inventor： Ki-chul Kim ,  Youn-soo Kim ,  Ki-vin Im ,  Cha-young Yoo ,  Jong-cheol Lee ,  Ki-yeon Park ,  Hoon-sang Choi ,  Se-hoon Oh

IPC: H01L21/30 ,  B08B3/00

CPC classification number: H01L21/314 ,  H01L21/02041 ,  H01L21/67034

Abstract: Provided are methods of removing water adsorbed or bonded to a surface of a semiconductor substrate, and methods of depositing an atomic layer using the method of removing water described herein. The method of removing water includes applying a chemical solvent to the surface of a semiconductor substrate, and removing the chemical solvent from the surface of the semiconductor substrate.

Abstract translation: 提供了除去吸附或结合到半导体衬底的表面的水的方法，以及使用本文所述除去水的方法沉积原子层的方法。 除去水的方法包括向半导体衬底的表面施加化学溶剂，并从半导体衬底的表面除去化学溶剂。

公开(公告)号：US20090154213A1

公开(公告)日：2009-06-18

申请号：US12347233

申请日：2008-12-31

Applicant: Nam-Seog KIM ,  Jong-Cheol LEE ,  Hak-Soo YU ,  Uk-Rae CHO

Inventor： Nam-Seog KIM ,  Jong-Cheol LEE ,  Hak-Soo YU ,  Uk-Rae CHO

IPC: G11C5/02 ,  G11C8/00 ,  G11C7/06 ,  G11C5/06

CPC classification number: G11C11/417 ,  G11C7/18 ,  G11C8/12

Abstract: A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.

公开(公告)号：US07500899B2

公开(公告)日：2009-03-10

申请号：US11263294

申请日：2005-10-31

Applicant: Min-Chul Sung ,  Bong-Hyun Kwon ,  Jae-Ho Oh ,  Won-Gu Choi ,  Jong-Cheol Lee

Inventor： Min-Chul Sung ,  Bong-Hyun Kwon ,  Jae-Ho Oh ,  Won-Gu Choi ,  Jong-Cheol Lee

IPC: A63H33/22 ,  A63H33/00

CPC classification number: B28B1/004 ,  B28B1/005 ,  B28B1/008 ,  C04B26/06 ,  C04B2111/545 ,  C04B2111/82 ,  C04B14/28 ,  C04B14/303 ,  C04B2103/54

Abstract: Disclosed herein are an artificial marble using multicolor chips, particularly striped chips, and a method for preparing the artificial marble. Since the artificial marble comprises multicolor chips in a new form together with conventional single-color chips, it enables achievement of various appearances, including designs and colors, thereby being highly differentiated from conventional artificial marbles containing combinations of single-color chips as well as displaying patterns and designs closely resembling natural granite.

Abstract translation: 本文公开了使用多色芯片，特别是条纹芯片的人造大理石和制备人造大理石的方法。 由于人造大理石由传统单色芯片组成的新型多色芯片组成，所以能够实现包括设计和颜色在内的各种外观，从而与包含单色芯片组合的常规人造大理石高度差异化，以及显示 图案和设计与天然花岗岩非常相似。

公开(公告)号：US20080203529A1

公开(公告)日：2008-08-28

申请号：US12034868

申请日：2008-02-21

Applicant: Sang-yeol Kang ,  Jong-cheol Lee ,  Ki-vin Lim ,  Hoon-sang Choi ,  Eun-ae Chung

Inventor： Sang-yeol Kang ,  Jong-cheol Lee ,  Ki-vin Lim ,  Hoon-sang Choi ,  Eun-ae Chung

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01L28/40 ,  H01L27/10852

Abstract: A semiconductor device including a multilayer dielectric film and a method for fabricating the semiconductor device are disclosed. The multilayer dielectric film includes a type-one dielectric film having a tetragonal crystalline structure, wherein the type-one dielectric film comprises a first substance. The multilayer dielectric film also comprises a type-two dielectric film also having a tetragonal crystalline structure, wherein the type-two dielectric film comprises a second substance different from the first substance and a dielectric constant of the type-two dielectric film is greater than a dielectric constant of the type-one dielectric film.

Abstract translation: 公开了一种包括多层介质膜的半导体器件和用于制造半导体器件的方法。 所述多层电介质膜包括具有四方晶系结构的一型电介质膜，其中，所述一型电介质膜包含第一物质。 所述多层绝缘膜还包括也具有四方晶系结构的二型电介质膜，其中所述二型电介质膜包括与所述第一物质不同的第二物质，并且所述二型电介质膜的介电常数大于 介电常数介电常数为1。

公开(公告)号：US20080122044A1

公开(公告)日：2008-05-29

申请号：US11865869

申请日：2007-10-02

Applicant: Sang-yeol KANG ,  Jong-cheol LEE ,  Ki-vin IM ,  Jae-hyun YEO ,  Hoon-sang CHOI ,  Eun-ae CHUNG

Inventor： Sang-yeol KANG ,  Jong-cheol LEE ,  Ki-vin IM ,  Jae-hyun YEO ,  Hoon-sang CHOI ,  Eun-ae CHUNG

IPC: H01L21/441 ,  H01L23/58

CPC classification number: H01L21/31641 ,  C23C16/405 ,  C23C16/45525 ,  C23C16/56 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31616 ,  H01L28/40

Abstract: A method of forming a dielectric layer in a capacitor adapted for use in a semiconductor device is disclosed. The method includes forming a first ZrO2 layer, forming an interfacial layer using a plasma treatment on the first ZrO2 layer, and forming a second ZrO2 layer on the interfacial layer.

Abstract translation: 公开了一种在适用于半导体器件的电容器中形成电介质层的方法。 该方法包括形成第一ZrO 2层，在第一ZrO 2层上使用等离子体处理形成界面层，并形成第二ZrO 2层， SUB>层。

公开(公告)号：US07338863B2

公开(公告)日：2008-03-04

申请号：US11311143

申请日：2005-12-20

Applicant: Jong-Cheol Lee ,  Jae-Hyoung Choi ,  Han-Mei Choi ,  Gab-Jin Nam ,  Young-Sun Kim

Inventor： Jong-Cheol Lee ,  Jae-Hyoung Choi ,  Han-Mei Choi ,  Gab-Jin Nam ,  Young-Sun Kim

IPC: H01L21/336

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/513 ,  H01L29/7881

Abstract: Example embodiments of the present invention disclose a non-volatile semiconductor memory device, which may include a dielectric layer having an enhanced dielectric constant. A tunnel oxide layer pattern and a floating gate may be sequentially formed on a substrate. A dielectric layer pattern including metal oxide doped with Group III transition metals may be formed on the floating gate using a pulsed laser deposition process. The dielectric layer pattern having an increased dielectric constant may be formed of metal oxide doped with a transition metal such as scandium, yttrium, or lanthanum.

Abstract translation: 本发明的示例实施例公开了一种非易失性半导体存储器件，其可以包括具有增强介电常数的介电层。 可以在衬底上依次形成隧道氧化物层图案和浮栅。 可以使用脉冲激光沉积工艺在浮栅上形成包括掺杂有III族过渡金属的金属氧化物的电介质层图案。 具有增加的介电常数的电介质层图案可以由掺杂有过渡金属如钪，钇或镧的金属氧化物形成。

公开(公告)号：US20070236863A1

公开(公告)日：2007-10-11

申请号：US11486065

申请日：2006-07-14

Applicant: Jong-cheol Lee ,  Young-sun Kim ,  Jung-hee Chung ,  Kyoung-ryul Yoon ,  Ki-vin Im ,  Jae-hyoung Choi

Inventor： Jong-cheol Lee ,  Young-sun Kim ,  Jung-hee Chung ,  Kyoung-ryul Yoon ,  Ki-vin Im ,  Jae-hyoung Choi

IPC: H01G4/06 ,  H01G7/00

CPC classification number: H01G4/10 ,  H01G4/33 ,  Y10T29/435

Abstract: A capacitor may have a pre-treatment layer formed on a lower electrode, reaction to a dielectric layer and/or deterioration of capacitor characteristics may be suppressed. At least part of the dielectric layer may be oxidized or nitridized after being oxidized, and increases in leakage current may be suppressed. In a method of fabricating a capacitor, a plasma treatment performed before and after the forming of the dielectric layer within the batch-type equipment may cause retention time between the plasma treatment and the deposition of the dielectric layer to be the same or substantially the same for each wafer and/or capacitors may show smaller variations in layer characteristics between wafers.

Abstract translation: 电容器可以具有形成在下电极上的预处理层，对电介质层的反应和/或电容器特性的劣化被抑制。 电介质层的至少一部分可以在被氧化后被氧化或氮化，并且可以抑制漏电流的增加。 在制造电容器的方法中，在分批式设备中形成电介质层之前和之后执行的等离子体处理可能导致等离子体处理和介电层沉积之间的保持时间相同或基本相同 对于每个晶片和/或电容器可以在晶片之间的层特性中显示较小的变化。

公开(公告)号：US20060217033A1

公开(公告)日：2006-09-28

申请号：US11263294

申请日：2005-10-31

Applicant: Min-Chul Sung ,  Bong-Hyun Kwon ,  Jae-Ho Oh ,  Won-Gu Choi ,  Jong-Cheol Lee

Inventor： Min-Chul Sung ,  Bong-Hyun Kwon ,  Jae-Ho Oh ,  Won-Gu Choi ,  Jong-Cheol Lee

IPC: A63H17/00

CPC classification number: B28B1/004 ,  B28B1/005 ,  B28B1/008 ,  C04B26/06 ,  C04B2111/545 ,  C04B2111/82 ,  C04B14/28 ,  C04B14/303 ,  C04B2103/54

Abstract: Disclosed herein are an artificial marble using multicolor chips, particularly striped chips, and a method for preparing the artificial marble. Since the artificial marble comprises multicolor chips in a new form together with conventional single-color chips, it enables achievement of various appearances, including designs and colors, thereby being highly differentiated from conventional artificial marbles containing combinations of single-color chips as well as displaying patterns and designs closely resembling natural granite.

公开(公告)号：US20060014384A1

公开(公告)日：2006-01-19

申请号：US11140552

申请日：2005-05-27

Applicant: Jong-Cheol Lee ,  Ki-Vin Im ,  Sung-Tae Kim ,  Young-Sun Kim ,  Cha-Young Yoo ,  Han-Mei Choi ,  Gab-Jin Nam ,  Seung-Hwan Lee

Inventor： Jong-Cheol Lee ,  Ki-Vin Im ,  Sung-Tae Kim ,  Young-Sun Kim ,  Cha-Young Yoo ,  Han-Mei Choi ,  Gab-Jin Nam ,  Seung-Hwan Lee

IPC: H01L21/20 ,  H01L21/44

CPC classification number: H01L21/0228 ,  C23C16/0245 ,  C23C16/4554 ,  C23C16/45546 ,  H01L21/02334 ,  H01L21/0234 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31637 ,  H01L21/31645 ,  H01L21/3185 ,  H01L28/40 ,  H01L28/90

Abstract: In a method of forming a layer using an atomic layer deposition process, after a substrate is loaded into a chamber, a first reactant is provided onto the substrate. The first reactant is partially chemisorbed on the substrate. A second reactant is introduced into the chamber to form a preliminary layer on the substrate by chemically reacting the second reactant with the chemisorbed first reactant. Impurities in the preliminary layer and unreacted reactants are simultaneously removed using a plasma for removing impurities to thereby form the layer on the substrate. The impurities in the layer may be effectively removed so that the layer may have reduced leakage current.

Abstract translation: 在使用原子层沉积工艺形成层的方法中，在将衬底装入腔室之后，在衬底上提供第一反应物。 第一反应物被部分化学吸附在基材上。 将第二反应物引入室中以通过使第二反应物与化学吸附的第一反应物发生化学反应在衬底上形成预备层。 使用用于除去杂质的等离子体同时除去预备层中的杂质和未反应的反应物，从而在基板上形成层。 可以有效地去除层中的杂质，使得该层可能具有减小的漏电流。