PRECISE MULTICAST TIMESTAMPING
    72.
    发明公开

    公开(公告)号:US20240089077A1

    公开(公告)日:2024-03-14

    申请号:US17942899

    申请日:2022-09-12

    CPC classification number: H04L7/0091 H04L12/1881

    Abstract: A network interface device includes a local register and packet processing circuitry coupled to the local register. The packet processing circuitry is to: capture a network packet transmitted by a software application running on an integrated computing system; capture, at time of transmission of the network packet, a value of a physical clock as a receive timestamp for subscriber entities that are running on the integrated computing system; store the receive timestamp in the local register; associate the receive timestamp from the local register with a first packet copy of the network packet; insert the first packet copy to a first receive pipeline of a first subscriber entity; associate the receive timestamp from the local register with a second packet copy of the network packet; and insert the second packet copy to a second receive pipeline of a second subscriber entity.

    Selective aggregation of messages in collective operations

    公开(公告)号:US20240086265A1

    公开(公告)日:2024-03-14

    申请号:US18074563

    申请日:2022-12-05

    Inventor: Richard Graham

    CPC classification number: G06F9/546

    Abstract: A method for collective communications includes invoking a collective operation over a group of computing processes in which the processes in the group concurrently transmit and receive data messages to and from other processes in the group via a communication medium. The processes detect respective sizes of the data messages and transmit the data messages for which the respective sizes are greater than a predefined threshold to respective destination processes in the group without aggregation. The data messages for which the respective sizes are less than the predefined threshold are aggregated, and the aggregated data messages are transmitted to the respective destination processes.

    MICE-ELEPHANT AWARE SHARED BUFFER SCHEMA
    74.
    发明公开

    公开(公告)号:US20240073151A1

    公开(公告)日:2024-02-29

    申请号:US17893835

    申请日:2022-08-23

    Abstract: A networking device and system are described, among other things. An illustrative system is disclosed to include a shared buffer and at least a flow controller. In some embodiments, the system and/or flow controller may be configured to measure a packet flow's bandwidth consumption of the shared buffer, assign a flow-type attribute to the packet flow based on the packet flow's bandwidth consumption of the shared buffer, select a shared buffer schema for the packet flow based on the flow-type attribute assigned to the packet flow, and apply the selected shared buffer schema to the packet flow. For example, the flow-type attribute assigned to the packet flow may comprise a mice flow state or an elephant flow state, and a reserve attribute may be assigned to the flow based on the packet flow being assigned the mice flow state or the elephant flow state.

    Flow-based congestion control
    75.
    发明公开

    公开(公告)号:US20240073141A1

    公开(公告)日:2024-02-29

    申请号:US17895108

    申请日:2022-08-25

    CPC classification number: H04L47/12 H04L47/30

    Abstract: A network device includes multiple ports, a Shared Buffer (SB) and a SB controller. The ports to connect to a communication network. The SB to temporarily store packets received from the communication network via the ports, the packets belonging to multiple flows. The SB controller to allocate one or more flow-specific storage regions in the SB, a given flow-specific storage region being allocated to store the packets that (i) belong to respective one or more of the flows and (ii) are to be transmitted via a respective egress queue. In response to detecting that an occupancy level in the given flow-specific storage region exceeds a specified occupancy threshold, the SB controller to report the flows in the given flow-specific storage region as congested.

    C2C YIELD AND PERFORMANCE OPTIMIZATION IN A DIE STACKING PLATFORM

    公开(公告)号:US20240071994A1

    公开(公告)日:2024-02-29

    申请号:US17895353

    申请日:2022-08-25

    CPC classification number: H01L25/0652 H01L23/481 H01L24/16 H01L2224/16225

    Abstract: Technologies for chip-to-chip (C2C) yield and performance optimization in a die stacking platform are described. One apparatus includes a substrate, a first integrated circuit disposed on the substrate at a first location, a second integrated circuit disposed on the substrate at a second location, and a third integrated circuit disposed on the second integrated circuit. The second integrated circuit is coupled to the first integrated circuit using a first chip-to-chip (C2C) interface via a physical terminal. The third integrated circuit is coupled to the first integrated circuit using a second C2C interface via the physical terminal. Only one of the first C2C interface and the second C2C interface is active at a time.

    Scalable synchronization of network devices

    公开(公告)号:US11917045B2

    公开(公告)日:2024-02-27

    申请号:US17871937

    申请日:2022-07-24

    CPC classification number: H04L7/0012

    Abstract: In one embodiment, a communication system includes network devices, each comprising a network interface to receive at least one data stream, a given network device being configured to recover a remote clock from the at least one data stream received by the given network device, a frequency synthesizer to generate a clock signal and output the clock signal to each of the network devices, wherein the given network device is configured to find a clock frequency differential between the clock signal and the recovered remote clock, and provide a control signal to the frequency synthesizer responsively to the clock frequency differential, the control signal causes the frequency synthesizer to adjust the clock signal so as to iteratively reduce an absolute value of the clock frequency differential between the clock signal and the recovered remote clock.

    Optimizing header-based action selection

    公开(公告)号:US11917042B2

    公开(公告)日:2024-02-27

    申请号:US17402545

    申请日:2021-08-15

    CPC classification number: H04L69/22

    Abstract: A network element includes one or more ports and a packet processor. The one or more ports are to transmit and receive packets over a network. The packet processor is to apply a plurality of rules to the packets, each rule specifying (i) expected values for each header field of a group of header fields of the packets, including, for a given header field in the group, at least a set of multiple expected values, (ii) a group ID associated with the set, and (iii) an action to be applied to the packets whose header fields match the expected values.

    Cryptographic data communication apparatus

    公开(公告)号:US11909855B2

    公开(公告)日:2024-02-20

    申请号:US18075460

    申请日:2022-12-06

    CPC classification number: H04L9/0625 H04L9/0861 H04L9/3247

    Abstract: In one embodiment, data communication apparatus includes packet processing circuitry to receive data from a memory responsively to a data transfer request, and cryptographically process the received data in units of data blocks using a block cipher so as to add corresponding cryptographically processed data blocks to a sequence of data packets, the sequence including respective ones of the cryptographically processed data blocks having block boundaries that are not aligned with payload boundaries of respective one of the packets, such that respective ones of the cryptographically processed data blocks are divided into two respective segments, which are contained in successive respective ones of the packets in the sequence, and a network interface which includes one or more ports for connection to a packet data network and is configured to send the sequence of data packets to a remote device over the packet data network via the one or more ports.

    TIME SYNCHRONIZED COLLECTIVE COMMUNICATION
    80.
    发明公开

    公开(公告)号:US20240056400A1

    公开(公告)日:2024-02-15

    申请号:US17886606

    申请日:2022-08-12

    CPC classification number: H04L47/56 H04L43/0894

    Abstract: Systems, methods, and devices that perform computing operations are provided. In one example, a system includes a least one node, the at least one node having one or more processors, each having associated memory, a clock, a scheduler, the scheduler monitoring one or more of rates, rates of lanes, rates at which packets are sent, times, latencies of packets, topology, communication states, nodes, and packets in the system, an attribute monitor that measures counters for one or more of congestion state, line rate, and communication attributes. A packet scheduler determines a destination node based on information from the scheduler and the attribute monitor, and sends at least a portion of a packet to the destination node.

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