公开(公告)号：US09978602B2

公开(公告)日：2018-05-22

申请号：US14923176

申请日：2015-10-26

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  STMICROELECTRONICS (Crolles 2) SAS ,  STMICROELECTRONICS SA

Inventor： Heimanu Niebojewski ,  Yves Morand ,  Maud Vinet

IPC: H01L21/84 ,  H01L21/28 ,  H01L29/66 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L21/28123 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02645 ,  H01L21/02667 ,  H01L21/76205 ,  H01L21/7624 ,  H01L21/76248 ,  H01L21/84 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78603

Abstract: The invention relates to a method for manufacturing a transistor comprising the preparation of a stack of layers of the semiconductor on insulator type comprising at least one substrate on which an insulating layer and an initial semiconductor layer are successively disposed. The method includes the formation of at least one oxide pad extending from a top face of the insulating layer, the formation of an additional layer made from semiconductor material covering the oxide pad and intended to form a channel for the transistor, the formation of a gate stack above the oxide pad, and the formation of a source and drain on either side of the gate stack.

公开(公告)号：US20180108762A1

公开(公告)日：2018-04-19

申请号：US15840890

申请日：2017-12-13

Applicant: STMicroelectronics SA

Inventor： Pascal Chevalier

IPC: H01L29/732 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L21/308 ,  H01L29/737

CPC classification number: H01L29/732 ,  H01L21/308 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/7371

Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening having sidewalls lined with an insulating sheath. A portion of the insulating sheath adjacent the base region is removed and a base contact region is formed by epitaxial material grown from a portion of the base region exposed by removal of the portion of the insulating sheath.

公开(公告)号：US20180106954A1

公开(公告)日：2018-04-19

申请号：US15730415

申请日：2017-10-11

Applicant: STMicroelectronics SA

Inventor： Folly Eli Ayi-Yovo ,  Cédric Durand ,  Frédéric Gianesello

IPC: F21V8/00 ,  G02B6/02 ,  G02B6/36

Abstract: The present invention relates to a method for manufacturing an optical device comprising forming a first trench in a glass plate and a second trench perpendicular to the first trench, wherein the first trench has an end opening into the second trench. The trenches are treated with hydrofluoric acid. The first trench is filled with a material to form a waveguide, and a mirror is formed on the wall of the second trench opposite the waveguide. An encapsulation layer is deposited over the glass plate, waveguide and second trench.

公开(公告)号：US20180097014A1

公开(公告)日：2018-04-05

申请号：US15722340

申请日：2017-10-02

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Vincent Barral ,  Nicolas Planes ,  Antoine Cros ,  Sebastien Haendler ,  Thierry Poiroux ,  Olivier Weber ,  Patrick Scheer

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  B82Y99/00

Abstract: An electronic chip includes FDSOI-type field-effect transistors. The transistor each have a channel region that is doped at an average level in a range from 1016 to 5*1017 atoms/cm3 with a conductivity type opposite to that of a conductivity type for the dopant in the drain and source regions.

公开(公告)号：US09929720B2

公开(公告)日：2018-03-27

申请号：US14847900

申请日：2015-09-08

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Thomas Quemerais ,  Alice Bossuet ,  Daniel Gloria

IPC: G01R1/067 ,  H03H11/24 ,  H03F3/60

CPC classification number: H03H11/245 ,  G01R1/06711 ,  H03F3/602 ,  H03F2200/211

Abstract: An attenuator includes: a first circuit including a common collector or common drain amplifier formed of a first transistor having its control node connected to an input of the attenuator and its emitter or source connected to an intermediate node of the attenuator; and a second circuit including a common collector or common drain amplifier formed of a second transistor having its emitter or source connected to the intermediate node and its control node connected to an output of the attenuator.

公开(公告)号：US20180083603A1

公开(公告)日：2018-03-22

申请号：US15462494

申请日：2017-03-17

Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

Inventor： Pascal Urard ,  Alok Kumar Tripathi

IPC: H03K3/356 ,  H03K19/00

CPC classification number: H03K3/356104 ,  H03K3/012 ,  H03K3/02335 ,  H03K3/35625 ,  H03K19/0002

Abstract: The synchronous retention flip-flop circuit comprises a first circuit module suitable for being powered by an interruptible power source and a second circuit module suitable for being powered by a permanent power source. The first circuit module includes first and second latch stages, which are configured to store at least one datum while said interruptible power source is supplying power, transmitting means suitable for being controlled by a second control signal and configured to deliver said at least one datum to the second circuit module before an interruption of said interruptible power source, the second circuit module being configured to preserve said at least one datum during said interruption, and restoring means suitable for being controlled by a first control signal and configured to restore said at least one datum at the end of said interruption. Only the second control signal remains active during interruption of the interruptible power source.

公开(公告)号：US09899366B2

公开(公告)日：2018-02-20

申请号：US15096975

申请日：2016-04-12

Applicant: STMicroelectronics SA

Inventor： Johan Bourgeat ,  Jean Jimenez

IPC: H01L29/66 ,  H01L27/02 ,  H01L29/74 ,  H01L29/744 ,  H01L29/10

CPC classification number: H01L27/0251 ,  H01L27/0262 ,  H01L29/1095 ,  H01L29/7436 ,  H01L29/744

Abstract: An electronic device is formed by a sequence of at least two thyristors coupled in series in a same conduction direction. Each thyristor has a gate of a first conductivity type. The gates of the first conductivity type for the thyristors in the sequence are coupled together in order to form a single control gate.

公开(公告)号：US09899217B2

公开(公告)日：2018-02-20

申请号：US14555897

申请日：2014-11-28

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  STMICROELECTRONICS SA

Inventor： Shay Reboh ,  Yves Morand ,  Hubert Moriceau

IPC: H01L21/02 ,  H01L21/762 ,  H01L21/84 ,  H01L29/10 ,  H01L21/265 ,  H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/02689 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02686 ,  H01L21/26506 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/7847 ,  H01L29/78654 ,  H01L29/78684

Abstract: A method is provided for producing a microelectronic device provided with different strained areas in a superficial layer of a semi-conductor on insulator type substrate, including amorphizing a region of the superficial layer and then a lateral recrystallization of the region from crystalline areas adjoining the region.

公开(公告)号：US20170356938A1

公开(公告)日：2017-12-14

申请号：US15357244

申请日：2016-11-21

Applicant: STMicroelectronics SA

Inventor： Bruno Delplanque

IPC: G01R22/10 ,  H04L7/00

CPC classification number: G01R22/10 ,  G01R21/133 ,  G01R31/31721 ,  G01R31/31727 ,  G06F1/324 ,  H04L7/0008

Abstract: A reference clock signal of at least one module clock signal associated with each module is delivered. A measurement period is generated and a module whose consumption is to be determined is selected. The frequency of the at least one module clock signal associated with the selected module reduced during the measurement period. A measurement of a first consumption of the device is made in the measurement period. A measurement of a second consumption of the device is made outside the measurement period. The consumption of the selected module is determined from the first and measured first and second consumptions.

公开(公告)号：US20170287618A1

公开(公告)日：2017-10-05

申请号：US15223148

申请日：2016-07-29

Applicant: STMICROELECTRONICS SA

Inventor： Vincent KNOPIK

IPC: H01F27/28 ,  H01F41/04 ,  H01F41/10 ,  H01F38/14 ,  H01Q1/48 ,  H01Q1/50 ,  H01Q1/36 ,  H01Q1/24 ,  H01Q7/00 ,  H01F27/29 ,  H03H7/42

CPC classification number: H01F27/2804 ,  H01F27/29 ,  H01F38/14 ,  H01F41/041 ,  H01F41/10 ,  H01F2027/2809 ,  H01F2027/2819 ,  H01L23/5227 ,  H01Q1/243 ,  H01Q1/36 ,  H01Q1/48 ,  H01Q1/50 ,  H01Q7/00 ,  H03H7/42

Abstract: A transformer of the symmetric-asymmetric type includes comprising a primary inductive circuit and a secondary inductive circuit formed in a same plane by respective interleaved and stacked metal tracks. A first crossing region includes a pair of connection plates facing one another, with each connection plate having a rectangular shape that is wider than the metal tracks, and diagonally connected to tracks of the secondary inductive circuit.