公开(公告)号：US20060148151A1

公开(公告)日：2006-07-06

申请号：US11029740

申请日：2005-01-04

申请人： Anand Murthy ,  Glenn Glass ,  Andrew Westmeyer ,  Michael Hattendorf ,  Jeffrey Wank

发明人： Anand Murthy ,  Glenn Glass ,  Andrew Westmeyer ,  Michael Hattendorf ,  Jeffrey Wank

IPC分类号： H01L21/8234

CPC分类号： H01L29/7848 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/517 ,  H01L29/66628 ,  H01L29/7834

摘要： This invention adds to the art of replacement source-drain cMOS transistors. Processes may involve etching a recess in the substrate material using one equipment set, then performing deposition in another. Disclosed is a method to perform the etch and subsequent deposition in the same reactor without atmospheric exposure. In-situ etching of the source-drain recess for replacement source-drain applications provides several advantages over state of the art ex-situ etching. Transistor drive current is improved by: (1) Eliminating contamination of the silicon-epilayer interface when the as-etched surface is exposed to atmosphere and (2) Precise control over the shape of the etch recess. Deposition may be done by a variety of techniques including selective and non-selective methods. In the case of blanket deposition, a measure to avoid amorphous deposition in performance critical regions is also presented.

公开(公告)号：US20060113634A1

公开(公告)日：2006-06-01

申请号：US11269477

申请日：2005-11-07

申请人： Shahriar Ahmed ,  Ravindra Soman ,  Anand Murthy ,  Mark Bohr

发明人： Shahriar Ahmed ,  Ravindra Soman ,  Anand Murthy ,  Mark Bohr

IPC分类号： H01L29/70

CPC分类号： H01L29/66287 ,  H01L29/42304 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

摘要： A bipolar transistor and its fabrication are described. The extrinsic base region is formed by growing a second, more heavily doped, epitaxial layer over a first epitaxial layer. The second layer extends under, and is insulated from, an overlying polysilicon emitter pedestal.

公开(公告)号：US20050230760A1

公开(公告)日：2005-10-20

申请号：US11152266

申请日：2005-06-13

申请人： Anand Murthy ,  Nayanee Gupta ,  Chris Auth ,  Glenn Glass

发明人： Anand Murthy ,  Nayanee Gupta ,  Chris Auth ,  Glenn Glass

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/76

CPC分类号： H01L29/66636 ,  H01L21/823418

摘要： Methods and associated apparatus of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising a region of higher active area density comprising source and drain recesses and a region of lower active area density comprising source and drain recesses, wherein the region of lower active area density further comprises dummy recesses, and selectively depositing a silicon alloy layer in the source, drain and dummy recesses to enhance the selectivity and uniformity of the silicon alloy deposition.

摘要翻译： 描述形成微电子结构的方法和相关装置。 那些方法包括提供一种衬底，其包括具有源极和漏极凹部的较高有源面积密度的区域和包括源极和漏极凹陷的较低有源面积密度的区域，其中较低有源面积密度的区域还包括虚设凹槽，并且选择性地沉积 源极，漏极和虚拟凹槽中的硅合金层，以增强硅合金沉积的选择性和均匀性。

公开(公告)号：US06952040B2

公开(公告)日：2005-10-04

申请号：US09895697

申请日：2001-06-29

申请人： Robert S. Chau ,  Jack Kavalieros ,  Anand Murthy ,  Brian Roberds ,  Brian S. Doyle

发明人： Robert S. Chau ,  Jack Kavalieros ,  Anand Murthy ,  Brian Roberds ,  Brian S. Doyle

IPC分类号： H01L21/3205 ,  H01L21/336 ,  H01L29/49 ,  H01L29/76 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/66772 ,  H01L29/41783 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/78654 ,  Y10S977/70 ,  Y10S977/721 ,  Y10S977/936

摘要： A novel transistor structure and its method of fabrication. According to the present invention, the transistor includes an intrinsic silicon body having a first surface. A gate dielectric is formed on the first surface of the intrinsic silicon body. A gate electrode is formed on the gate dielectric wherein the gate electrode comprises a mid-gap work function film on the gate dielectric. A pair of source/drain regions are formed on opposite sides of the intrinsic silicon body.

摘要翻译： 一种新颖的晶体管结构及其制造方法。 根据本发明，晶体管包括具有第一表面的本征硅体。 在本征硅体的第一表面上形成栅极电介质。 栅极电极形成在栅极电介质上，其中栅电极在栅极电介质上包括中间间隙功函数膜。 一对源极/漏极区域形成在本征硅体的相对侧上。

公开(公告)号：US20050184311A1

公开(公告)日：2005-08-25

申请号：US11107141

申请日：2005-04-14

申请人： Anand Murthy ,  Robert Chau ,  Tahir Ghani ,  Kaizad Mistry

发明人： Anand Murthy ,  Robert Chau ,  Tahir Ghani ,  Kaizad Mistry

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/165 ,  H01L29/78 ,  H01L29/739

CPC分类号： H01L29/7848 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7842

摘要： A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

摘要翻译： 描述了用于制造改进的PMOS半导体晶体管的工艺。 凹陷被蚀刻成一层外延硅。 源极和漏极膜沉积在凹槽中。 源极和漏极膜由硅和锗的合金制成。 合金外延沉积在硅层上。 合金因此具有与硅层的晶格结构相同结构的晶格。 然而，由于包含锗，合金的晶格具有比硅层的晶格间隔更大的间隔。 较大的间距在源极和漏极膜之间的晶体管的沟道中产生应力。 应力增加晶体管的IATAT和/或DLIN 。 可以通过包括碳而不是锗来以类似的方式制造NMOS晶体管，从而产生拉伸应力。

公开(公告)号：US06927140B2

公开(公告)日：2005-08-09

申请号：US10225586

申请日：2002-08-21

申请人： Ravindra Soman ,  Anand Murthy

发明人： Ravindra Soman ,  Anand Murthy

IPC分类号： H01L21/205 ,  H01L21/331 ,  H01L29/10 ,  H01L21/8222

CPC分类号： H01L29/1004 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/66242

摘要： A method for forming a base of a bipolar transistor. A narrow base is formed using a flash of boron doping gas in a reaction chamber to create a narrow base with high boron concentration. This method allows for reliable formation of a base with high boron concentration while maintaining manageability in controlling deposition of other materials in a substrate.

摘要翻译： 一种用于形成双极晶体管的基极的方法。 在反应室中使用硼掺杂气体的闪光形成窄碱以产生具有高硼浓度的窄碱。 该方法允许可靠地形成具有高硼浓度的碱，同时保持控制其它材料在衬底中沉积的可管理性。

公开(公告)号：US20050104160A1

公开(公告)日：2005-05-19

申请号：US10715971

申请日：2003-11-17

申请人： Shahriar Ahmed ,  Ravindra Soman ,  Anand Murthy ,  Mark Bohr

发明人： Shahriar Ahmed ,  Ravindra Soman ,  Anand Murthy ,  Mark Bohr

IPC分类号： H01L21/331 ,  H01L29/423 ,  H01L29/732 ,  H01L29/737 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/70 ,  H01L31/11

CPC分类号： H01L29/66287 ,  H01L29/42304 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

摘要： A bipolar transistor and its fabrication are described. The extrinsic base region is formed by growing a second, more heavily doped, epitaxial layer over a first epitaxial layer. The second layer extends under, and is insulated from, an overlying polysilicon emitter pedestal.

摘要翻译： 描述了双极晶体管及其制造。 通过在第一外延层上生长第二更重掺杂的外延层来形成非本征基区。 第二层在覆盖多晶硅发射器基座的下方延伸并与其绝缘。

公开(公告)号：US06373112B1

公开(公告)日：2002-04-16

申请号：US09454056

申请日：1999-12-02

申请人： Anand Murthy ,  Robert S. Chau

发明人： Anand Murthy ,  Robert S. Chau

IPC分类号： H01L2976

CPC分类号： H01L21/2807

摘要： An insulated gate field effect transistor (FET) of a particular conductivity type, has as a gate electrode including a polycrystalline SiGe layer. A process in accordance with the present invention includes forming an ultra-thin silicon seed film superjacent a gate dielectric layer followed by forming a SiGe layer over the seed layer. The thin Si seed layer enables deposition of the SiGe film to be substantially uniform and continuous without significant gate oxide degradation. The small thickness of the seed layer also enables effective Ge diffusion into the Si seed layer during subsequent deposition and/or subsequent thermal operations, resulting in a homogenous Ge concentration in the seed film and the SiGe overlayer.

摘要翻译： 具有特定导电类型的绝缘栅场效应晶体管（FET）具有包括多晶SiGe层的栅电极。 根据本发明的方法包括在栅极电介质层之上形成超薄硅籽晶膜，然后在晶种层上形成SiGe层。 薄Si种子层能够使SiGe膜的沉积基本上均匀且连续，而不会显着的栅极氧化物降解。 籽晶层的厚度也使得在随后的沉积和/或随后的热操作期间能够有效地将Ge扩散到Si籽晶层中，导致种子膜和SiGe覆盖层中均匀的Ge浓度。

公开(公告)号：US20140264280A1

公开(公告)日：2014-09-18

申请号：US13996848

申请日：2013-03-15

申请人： Seiyon Kim ,  Daniel Aubertine ,  Kelin Kuhn ,  Anand Murthy

发明人： Seiyon Kim ,  Daniel Aubertine ,  Kelin Kuhn ,  Anand Murthy

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

摘要： A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures andor drain the structures, when the material used in the fabrication of the source structures andor the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures andor the drain structures may be prevented.

摘要翻译： 本描述的纳米线器件可以通过结合在制造至少一个纳米线晶体管期间形成的至少一个底层蚀刻停止来产生，以便有助于保护源结构和/或漏极结构免受可能由制造产生的损伤 过程。 当用于制造源结构的材料和漏极结构易于被用于去除牺牲材料的工艺被蚀刻时，底层蚀刻停止件可以防止对源结构的损坏和排出结构，即低 选择性地连接到源极结构和/或漏极结构材料，使得可以防止晶体管栅电极和为源结构形成的触点之间的电位短路以及漏极结构。

公开(公告)号：US20120032265A1

公开(公告)日：2012-02-09

申请号：US13020945

申请日：2011-02-04

申请人： Danielle Simonelli ,  Anand Murthy

发明人： Danielle Simonelli ,  Anand Murthy

IPC分类号： H01L29/772

CPC分类号： H01L21/0245 ,  H01L21/02381 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/517 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/785

摘要： Embodiments of an apparatus and methods for providing a graded high germanium compound region are generally described herein. Other embodiments may be described and claimed.

摘要翻译： 本文通常描述用于提供渐变的高锗化合物区域的装置和方法的实施例。 可以描述和要求保护其他实施例。