公开(公告)号：US08084142B2

公开(公告)日：2011-12-27

申请号：US11525762

申请日：2006-09-21

申请人： Cem Basceri ,  Gurtej S. Sandhu ,  H. Montgomery Manning

发明人： Cem Basceri ,  Gurtej S. Sandhu ,  H. Montgomery Manning

IPC分类号： H01L21/44 ,  H01L21/4763 ,  H01L29/40

CPC分类号： H01L21/76823 ,  H01L21/28512 ,  H01L21/76895 ,  Y10T428/12542

摘要： The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.

摘要翻译： 本发明包括形成对场效应晶体管的源极/漏极区的导电接触的方法，以及形成局部互连的方法。 在一个实施方案中，形成到场效应晶体管的源/漏区的导电接触的方法包括在晶体管栅极和场效应晶体管的沟道区之间提供栅介质材料。 至少一些栅极电介质材料延伸以在场效应晶体管的至少一个源极/漏极区域上接收。 接收在一个源极/漏极区域上的栅极电介质材料暴露于有效地将其从电绝缘转变为导电并与一个源极/漏极区域导电接触的条件。 考虑了其他方面和实现。

公开(公告)号：US08003542B2

公开(公告)日：2011-08-23

申请号：US12489337

申请日：2009-06-22

申请人： Sanket Sant ,  Gurtej S. Sandhu ,  Neal R. Rueger

发明人： Sanket Sant ,  Gurtej S. Sandhu ,  Neal R. Rueger

IPC分类号： H01L21/302

CPC分类号： H01L21/3088 ,  H01L21/0337 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/76802 ,  H01L27/1052

摘要： Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed around a plurality of mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one of the materials are then etched, leaving behind vertically-extending layers formed of the other of the materials, which form a mask pattern. Alternatively, instead of depositing alternating layers, amorphous carbon is deposited around the remaining spacers followed by a plurality of cycles of forming pairs of spacers on the amorphous carbon, removing one of the pairs of spacers and depositing an amorphous carbon layer. The cycles can be repeated to form the desired pattern. Because the critical dimensions of some features in the pattern can be set by controlling the width of the spaces between spacers, exceptionally small mask features can be formed.

摘要翻译： 使用多个间距倍数的间隔物来形成具有特别小的临界尺寸的特征的掩模图案。 去除围绕多个心轴形成的每对间隔件中的一个，并且由两个相互选择性可蚀刻的材料形成的交替层围绕剩余的间隔物沉积。 然后蚀刻由一种材料形成的层，留下由形成掩模图案的另一种材料形成的垂直延伸层。 或者，代替沉积交替层，无定形碳沉积在剩余的间隔物周围，随后在无定形碳上形成一对间隔物的多个循环，去除一对隔离物中的一个并沉积无定形碳层。 可以重复循环以形成所需的图案。 由于图案中的某些特征的临界尺寸可以通过控制间隔物之间​​的间隔的宽度来设定，所以可以形成特别小的掩模特征。

公开(公告)号：US20110139368A1

公开(公告)日：2011-06-16

申请号：US13031022

申请日：2011-02-18

申请人： Mark J. Williamson ,  Gurtej S. Sandhu ,  Justin R. Arrington

发明人： Mark J. Williamson ,  Gurtej S. Sandhu ,  Justin R. Arrington

IPC分类号： H01L21/306

CPC分类号： H01L22/14 ,  G01R31/2898 ,  H01J37/252 ,  H01J37/28 ,  H01J37/3056 ,  H01J2237/24564 ,  H01J2237/24592

摘要： Apparatus and systems provide a mechanism to examine physical properties and/or diagnose problems at a selected location of an integrated circuit. Such apparatus and systems can include a source of an energetic beam directed at the selected location. The apparatus and systems may be used to provide examination and/or diagnostic methods that may be used in areas smaller than one micron in diameter and that may be used to remove IC layers, either selectively or non-selectively, until a desired depth is obtained.

摘要翻译： 装置和系统提供了一种检查在集成电路的选定位置处的物理特性和/或诊断问题的机制。 这样的装置和系统可以包括指向所选位置的能量束的源。 该装置和系统可用于提供可用于直径小于1微米的区域的检查和/或诊断方法，并且可用于选择性地或非选择性地去除IC层，直到获得期望的深度 。

公开(公告)号：US07923308B2

公开(公告)日：2011-04-12

申请号：US11478715

申请日：2006-06-30

申请人： Cem Basceri ,  Gurtej S. Sandhu ,  H. Montgomery Manning

发明人： Cem Basceri ,  Gurtej S. Sandhu ,  H. Montgomery Manning

IPC分类号： H01L21/332 ,  H01L21/336 ,  H01L21/4763

CPC分类号： H01L21/76823 ,  H01L21/28512 ,  H01L21/76895 ,  Y10T428/12542

摘要： The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.

公开(公告)号：US20100267240A1

公开(公告)日：2010-10-21

申请号：US12827506

申请日：2010-06-30

申请人： Gurtej S. Sandhu ,  Kirk D. Prall

发明人： Gurtej S. Sandhu ,  Kirk D. Prall

IPC分类号： H01L21/302 ,  C23F1/08

CPC分类号： H01L21/67063 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/32053 ,  H01L21/32134

摘要： Spacers in a pitch multiplication process are formed without performing a spacer etch. Rather, the mandrels are formed over a substrate and then the sides of the mandrels are reacted, e.g., in an oxidization, nitridation, or silicidation step, to form a material that can be selectively removed relative to the unreacted portions of the mandrel. The unreacted portions are selectively removed to leave a pattern of free-standing spacers. The free-standing spacers can serve as a mask for subsequent processing steps, such as etching the substrate.

摘要翻译： 在不执行间隔物蚀刻的情况下形成间距倍增过程中的间隔物。 相反，心轴形成在衬底上，然后心轴的侧面例如在氧化，氮化或硅化步骤中反应，以形成相对于心轴的未反应部分可以选择性去除的材料。 选择性地去除未反应部分以留下独立间隔物的图案。 独立的间隔物可以用作后续处理步骤的掩模，例如蚀刻基底。

公开(公告)号：US20100258857A1

公开(公告)日：2010-10-14

申请号：US12820924

申请日：2010-06-22

申请人： Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Cem Basceri ,  Eric R. Blomiley

发明人： Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Cem Basceri ,  Eric R. Blomiley

IPC分类号： H01L29/78

CPC分类号： H01L29/66787 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/66742 ,  H01L29/78642

摘要： This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon comprises epitaxially growing a silicon-comprising layer from an exposed monocrystalline material. The epitaxially grown silicon comprises at least one of carbon, germanium, and oxygen present at a total concentration of no greater than 1 atomic percent. In one implementation, the layer comprises a silicon germanium alloy comprising at least 1 atomic percent germanium, and further comprises at least one of carbon and oxygen at a total concentration of no greater than 1 atomic percent. Other aspects and implementations are contemplated.

摘要翻译： 本发明包括形成包括外延硅和场效应晶体管的层的方法。 在一个实施方案中，形成包含外延硅的层的方法包括从暴露的单晶材料外延生长含硅层。 外延生长的硅包括以不超过1原子％的总浓度存在的碳，锗和氧中的至少一种。 在一个实施方案中，该层包括含有至少1原子％锗的硅锗合金，并且还包含总浓度不大于1原子％的碳和氧中的至少一种。 考虑了其他方面和实现。

公开(公告)号：US07811840B2

公开(公告)日：2010-10-12

申请号：US12128334

申请日：2008-05-28

申请人： Gurtej S. Sandhu ,  Bhaskar Srinivasan

发明人： Gurtej S. Sandhu ,  Bhaskar Srinivasan

IPC分类号： H01L21/00

CPC分类号： H01L45/00 ,  Y10S257/91 ,  Y10S438/90 ,  Y10S438/902 ,  Y10S438/983

摘要： Some embodiments include methods of forming diodes. The methods may include oxidation of an upper surface of a conductive electrode to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of an oxidizable material over a conductive electrode, and subsequent oxidation of the oxidizable material to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of a metal halide layer over a conductive electrode. Some embodiments include diodes that contain a metal halide layer between a pair of diode electrodes.

摘要翻译： 一些实施例包括形成二极管的方法。 所述方法可以包括氧化导电电极的上表面以在导电电极上形成氧化物层。 在一些实施方案中，所述方法可包括在导电电​​极上形成可氧化材料，以及随后氧化可氧化材料以在导电电极上形成氧化物层。 在一些实施例中，所述方法可包括在导电电​​极上形成金属卤化物层。 一些实施例包括在一对二极管电极之间包含金属卤化物层的二极管。

公开(公告)号：US20100248094A1

公开(公告)日：2010-09-30

申请号：US12797508

申请日：2010-06-09

申请人： William Stanton ,  Gurtej S. Sandhu

发明人： William Stanton ,  Gurtej S. Sandhu

IPC分类号： G03F1/00

CPC分类号： G03F1/72 ,  G03F1/50

摘要： Some embodiments include methods of treating reticles to provide backside masking across regions of the reticle to compensate for problems occurring during photolithographic processing. The problems may be, for example, defects in the reticle, problems associated with deposition or development of photoresist, or problems associated with substrate topography. The masking may alter one or both of transmission of electromagnetic radiation through the masked regions, and polarization of electromagnetic radiation passed through the masked regions. Some embodiments include reticles having patterns along front sides for patterning electric magnetic radiation, and masks across portions of the backsides to at least partially block transmission of electromagnetic radiation through portions of the patterns.

摘要翻译： 一些实施例包括处理掩模版以在掩模版的区域之间提供背面掩蔽以补偿光刻处理期间出现的问题的方法。 问题可能是例如掩模版中的缺陷，与光致抗蚀剂的沉积或显影相关的问题，或与衬底形貌有关的问题。 掩蔽可以改变透过屏蔽区域的电磁辐射的一种或两种以及通过掩蔽区域的电磁辐射的极化。 一些实施例包括具有沿着前侧的图案的掩模版，用于图形化电磁辐射，以及掩模跨越所述背面的部分以至少部分地阻挡电磁辐射通过所述图案的一部分的透射。

公开(公告)号：US07791055B2

公开(公告)日：2010-09-07

申请号：US11483800

申请日：2006-07-10

申请人： Mark J. Williamson ,  Paul M. Johnson ,  Shawn D. Lyonsmith ,  Gurtej S. Sandhu ,  Justin R. Arrington

发明人： Mark J. Williamson ,  Paul M. Johnson ,  Shawn D. Lyonsmith ,  Gurtej S. Sandhu ,  Justin R. Arrington

IPC分类号： G01N21/86

CPC分类号： G01N1/32

摘要： A method of imaging and identifying defects and contamination on the surface of an integrated circuit is described. The method may be used on areas smaller than one micron in diameter. An energetic beam, such as an electron beam, is directed at a selected IC location having a layer of a solid, fluid or gaseous reactive material formed over the surface. The energetic beam disassociates the reactive material in the region into chemical radicals that either chemically etch the surface preferentially, or deposit a thin layer of a conductive material over the local area around the energetic beam. The surface may be examined as various layers are selectively etched to decorate defects and/or as various layers are locally deposited in the area around the energetic beam. SEM imaging and other analytic methods may be used to identify the problem more easily.

摘要翻译： 描述了在集成电路的表面上成像和识别缺陷和污染的方法。 该方法可以用于直径小于1微米的区域。 诸如电子束的能量束被引导到选定的IC位置，其具有形成在表面上的固体，流体或气态反应性材料层。 能量束将该区域中的反应性材料分解成化学自由基，其优先化学蚀刻表面，或者在能量束周围的局部区域上沉积导电材料的薄层。 可以检查表面，因为选择性地蚀刻各种层以修饰缺陷和/或当各种层局部沉积在能量束周围的区域中时。 可以使用SEM成像和其他分析方法来更容易地识别问题。

公开(公告)号：US07776744B2

公开(公告)日：2010-08-17

申请号：US11219346

申请日：2005-09-01

申请人： Gurtej S. Sandhu ,  Kirk D. Prall

发明人： Gurtej S. Sandhu ,  Kirk D. Prall

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/67063 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/32053 ,  H01L21/32134

摘要： Spacers in a pitch multiplication process are formed without performing a spacer etch. Rather, the mandrels are formed over a substrate and then the sides of the mandrels are reacted, e.g., in an oxidization, nitridation, or silicidation step, to form a material that can be selectively removed relative to the unreacted portions of the mandrel. The unreacted portions are selectively removed to leave a pattern of free-standing spacers. The free-standing spacers can serve as a mask for subsequent processing steps, such as etching the substrate.

摘要翻译： 在不执行间隔物蚀刻的情况下形成间距倍增过程中的间隔物。 相反，心轴形成在衬底上，然后心轴的侧面例如在氧化，氮化或硅化步骤中反应，以形成相对于心轴的未反应部分可以选择性去除的材料。 选择性地去除未反应部分以留下独立间隔物的图案。 独立的间隔物可以用作后续处理步骤的掩模，例如蚀刻基底。