Lubricant applicator and image forming apparatus including same
    73.
    发明授权
    Lubricant applicator and image forming apparatus including same 有权
    润滑剂涂布器和包括其的成像设备

    公开(公告)号:US07953363B2

    公开(公告)日:2011-05-31

    申请号:US12571640

    申请日:2009-10-01

    IPC分类号: G03G21/00

    CPC分类号: F16N7/24

    摘要: A lubricant applicator includes a solid mold lubricant, a lubricant application roller, and a flicker member. The lubricant application roller scrapes and applies the lubricant to an image bearing member. The flicker member removes a powder substance adhered to the surface of the lubricant application roller and is disposed upstream of the solid mold lubricant in a direction of rotation of the lubricant application roller. The lubricant application roller, the flicker member, and the solid mold lubricant define a sealed space therebetween. A lubricant applicator includes the solid mold lubricant, the lubricant application roller, the flicker member, and an adherence prevention member that prevents the substance removed by the flicker member from adhering again to the lubricant application roller. A lubricant applicator includes the solid mold lubricant, the lubricant application roller, and a lubricant receiver that receives the scraped lubricant from the lubricant application roller.

    摘要翻译: 润滑剂涂布器包括固体模具润滑剂,润滑剂施加辊和闪烁构件。 润滑剂施加辊刮擦并将润滑剂施加到图像承载部件上。 闪烁部件除去附着在润滑剂涂布辊的表面上的粉末物质,并且在润滑剂涂布辊的旋转方向上设置在固体润滑剂的上游。 润滑剂涂布辊,闪光部件和实心模具润滑剂在其间形成密封空间。 润滑剂涂布器包括固体模具润滑剂,润滑剂施加辊,闪烁构件和防止由闪烁构件去除的物质再次粘附到润滑剂施加辊上的防粘附构件。 润滑剂涂抹器包括固体模具润滑剂,润滑剂施加辊和从润滑剂施加辊接收刮擦的润滑剂的润滑剂接收器。

    Memory system
    74.
    发明授权
    Memory system 有权
    内存系统

    公开(公告)号:US08755233B2

    公开(公告)日:2014-06-17

    申请号:US13240014

    申请日:2011-09-22

    摘要: According to one embodiment, there is provided memory system including a non-volatile memory device, a monitoring unit, and a changing unit. The non-volatile memory device stores data. The monitoring unit monitors a characteristic of the non-volatile memory device when writing and erasing processes are performed to write and erase the data to and from the non-volatile memory device. The changing unit changes at least one of a value of a writing start voltage and an increase width of a writing voltage in the writing process in accordance with the monitored characteristic so that a time for the writing process is substantially identical to a target value. The writing process is a process in which a writing operation and a verification operation are alternately repeated.

    摘要翻译: 根据一个实施例,提供了包括非易失性存储器件,监视单元和改变单元的存储器系统。 非易失性存储器件存储数据。 当执行写入和擦除处理时,监视单元监视非易失性存储器件的特性,以向非易失性存储器件写入和擦除数据。 改变单元根据所监视的特性改变写入开始电压的值和写入电压的增加宽度中的至少一个,使得写入处理的时间与目标值基本相同。 写入处理是交替重复写入操作和验证操作的处理。

    Nonvolatile semiconductor memory device
    75.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号:US08575590B2

    公开(公告)日:2013-11-05

    申请号:US13038771

    申请日:2011-03-02

    IPC分类号: H01L47/00 H01L27/10 H01L29/06

    摘要: According to one embodiment, there is provided a nonvolatile semiconductor memory device including a first interconnection layer, memory cell modules each of which is formed by laminating a non-ohmic element layer with an MIM structure having an insulating film sandwiched between metal films and a variable resistance element layer, and a second interconnection layer formed on the memory cell modules, the insulating film of the non-ohmic element layer includes plural layers whose electron barriers and dielectric constants are different, or contains impurity atoms that form defect levels in the insulating film or contains semiconductor or metal dots. The nonvolatile semiconductor memory device using non-ohmic elements and variable resistance elements in which memory cells can be miniaturized and formed at low temperatures is realized by utilizing the above structures.

    摘要翻译: 根据一个实施例,提供了一种非易失性半导体存储器件,其包括第一互连层,存储单元模块,每个存储单元模块通过层叠具有MIM结构的非欧姆元件层而形成,所述MIM结构具有夹在金属膜之间的绝缘膜和可变 电阻元件层和形成在存储单元模块上的第二互连层,非欧姆元件层的绝缘膜包括其电子势垒和介电常数不同的多个层,或包含在绝缘膜中形成缺陷水平的杂质原子 或包含半导体或金属点。 通过利用上述结构,实现了使用非欧姆元件和可变电阻元件的非易失性半导体存储器件,其中存储单元可以在低温下小型化并形成。

    Semiconductor memory device
    76.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号:US08441040B2

    公开(公告)日:2013-05-14

    申请号:US12886090

    申请日:2010-09-20

    IPC分类号: H01L23/52

    摘要: A semiconductor memory device according to an embodiment includes: a cell array block having, above a semiconductor substrate, a plurality of first and second wirings intersecting with one another, and a plurality of memory cells, the first and second wirings being separately formed in a plurality of layers in a perpendicular direction to the semiconductor substrate; and a first via wiring, connecting the first wiring in an n1-th layer of the cell array block with the first wiring in an n2-th layer, the semiconductor substrate or another metal wiring, and extending in a laminating direction of the cell array block. The first via wiring has a cross section orthogonal to the laminating direction of the cell array block. The cross section has an elliptical shape and a longer diameter in a direction perpendicular to the first wiring direction.

    摘要翻译: 根据实施例的半导体存储器件包括:单元阵列块,其在半导体衬底上方具有彼此相交的多个第一和第二布线,以及多个存储单元,所述第一和第二布线分别形成在 在与半导体衬底垂直的方向上的多个层; 以及第一通孔布线,将第一电极阵列块的第n1层中的第一布线与第n2层的第一布线,半导体基板或其他金属布线连接,并且在电池阵列的层叠方向上延伸 块。 第一通孔布线具有与单元阵列块的层叠方向正交的截面。 横截面在垂直于第一布线方向的方向上具有椭圆形状和较长直径。

    Semiconductor memory device and method of manufacturing the same
    77.
    发明授权
    Semiconductor memory device and method of manufacturing the same 有权
    半导体存储器件及其制造方法

    公开(公告)号:US08222677B2

    公开(公告)日:2012-07-17

    申请号:US12399376

    申请日:2009-03-06

    IPC分类号: H01L29/00

    摘要: A semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each comprising a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of contact plugs extending in the stack direction of the cell array layers to connect between the first lines, between the second lines, between the first or second line and the semiconductor substrate, or between the first or second line and another metal line, in the cell array layers. The first or second line in a certain one of the cell array layers has a contact connector making contact with both sides of the contact plug.

    摘要翻译: 半导体存储器件包括半导体衬底; 形成在所述半导体衬底上的单元阵列块,并且包括多个堆叠的单元阵列层,每个堆叠的单元阵列层包括多个第一线,与所述多条第一线交叉的多个第二线,以及连接在所述第一和第二线之间的第一和第二线的交点处的存储单元 线条 以及在单元阵列层的堆叠方向上延伸的多个接触插塞,以在第一线之间,第二线之间,第一线或第二线与半导体衬底之间,或第一线或第二线与另一金属线之间连接 ,在单元阵列层。 电池阵列层中某一个的第一或第二线具有与接触插塞的两侧接触的接触连接器。

    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
    78.
    发明申请
    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
    非易失性半导体存储器件

    公开(公告)号:US20120002475A1

    公开(公告)日:2012-01-05

    申请号:US13232163

    申请日:2011-09-14

    IPC分类号: G11C16/04

    摘要: A non-volatile semiconductor memory device includes a non-volatile memory having a plurality of blocks each including a plurality of memory cells, a bit line electrically connected to one end of a current path of the memory cell, a source line electrically connected to the other end of the current path of the memory cell, a word line electrically connected to the gate electrode, a sense amplifier circuit electrically connected to the bit line and configured to read data from the memory cell, a row decoder electrically connected to the word line and configured to apply a read voltage at which the memory cell is set to an ON state to the word line, and a controller configured to measure a cell current flowing through the memory cell in the ON state to judge whether the memory cell has been degraded.

    摘要翻译: 非挥发性半导体存储器件包括具有多个块的非易失性存储器,每个块包括多个存储器单元,电连接到存储单元的电流路径的一端的位线,电连接到存储单元的源极线 存储单元的电流路径的另一端,电连接到栅电极的字线,电连接到位线并被配置为从存储单元读取数据的读出放大器电路,电连接到字线的行解码器 并且被配置为将存储单元设置为ON状态的读取电压施加到字线,以及控制器,被配置为测量在ON状态下流过存储单元的单元电流,以判断存储单元是否已经劣化 。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    79.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
    非易失性半导体存储器件

    公开(公告)号:US20110242875A1

    公开(公告)日:2011-10-06

    申请号:US13058952

    申请日:2009-06-24

    IPC分类号: G11C11/00

    摘要: A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells arranged in matrix and connected at intersections of the first and second lines between both lines, each memory cell containing a serial circuit of an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data and a non-ohmic element; and a plurality of access circuits operative to simultaneously access the memory cells physically separated from each other in the cell array.

    摘要翻译: 一种非易失性半导体存储器件,包括一个单元阵列,该单元阵列包括多个第一线,与该多条第一线相交的多个第二线,以及多个存储单元,被布置成矩阵并连接在两条线之间的第一和第二线的交点处 每个存储单元包含其中电阻被非易失性地存储为数据的电可擦除可编程可变电阻元件和非欧姆元件的串行电路; 以及多个访问电路,其操作以同时访问在单元阵列中彼此物理分离的存储单元。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    80.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
    非易失性半导体存储器件

    公开(公告)号:US20100328988A1

    公开(公告)日:2010-12-30

    申请号:US12677017

    申请日:2008-09-09

    IPC分类号: G11C11/00

    摘要: A nonvolatile semiconductor memory device comprises a memory cell array of electrically erasable programmable nonvolatile memory cells arranged in matrix, each memory cell using a variable resistor. A pulse generator is operative to generate plural types of write pulses for varying the resistance of the variable resistor in three or more stages based on ternary or higher write data. A selection circuit is operative to select a write target memory cell from the memory cell array based on a write address and supply the write pulse generated from the pulse generator to the selected memory cell.

    摘要翻译: 非易失性半导体存储器件包括以矩阵形式布置的电可擦除可编程非易失性存储单元的存储单元阵列,每个存储单元使用可变电阻器。 脉冲发生器用于产生多种类型的写入脉冲,用于基于三进制或更高写入数据在三个或更多个阶段中改变可变电阻器的电阻。 选择电路可操作以基于写地址从存储单元阵列中选择写入目标存储单元,并将从脉冲发生器产生的写入脉冲提供给所选存储单元。