公开(公告)号：US20190198569A1

公开(公告)日：2019-06-27

申请号：US16221385

申请日：2018-12-14

申请人： Fu-Chang Hsu

发明人： Fu-Chang Hsu

IPC分类号： H01L27/24 ,  H01L27/22 ,  H01L45/00

CPC分类号： H01L27/249 ,  H01L27/224 ,  H01L27/2409 ,  H01L45/1226 ,  H01L45/126 ,  H01L45/146 ,  H01L45/1683

摘要： Three-dimensional vertical memory array cell structures and processes. In an exemplary embodiment, a 3D vertical memory array structure is formed by performing operations that include forming an array stack having alternating metal layers and insulator layers, forming a hole through the array stack to expose internal surfaces of the metal layers and internal surfaces of the insulator layers, and performing a metal-oxidation process on the internal surfaces of the metal layers to form selector devices on the internal surfaces of the metal layers. The operations also include depositing one of resistive material or phase-change material within the hole on the selector devices and the internal surfaces of the insulator layers, such that the hole is reduced to a smaller hole, and depositing conductor material in the smaller hole.

公开(公告)号：US20180157964A1

公开(公告)日：2018-06-07

申请号：US15821679

申请日：2017-11-22

申请人： Fu-Chang Hsu ,  Kevin Hsu

发明人： Fu-Chang Hsu ,  Kevin Hsu

IPC分类号： G06N3/04 ,  G06N3/063

CPC分类号： G06N3/04 ,  G06N3/063

摘要： A high-density neural network array. In an exemplary embodiment, an apparatus includes a three-dimensional (3D) structure having a plurality of layers forming a neural network. Each layer comprises one or more conductors forming neurons with each neuron having neuron inputs and neuron outputs. The apparatus also includes synapse elements coupled between the neurons outputs and the neuron inputs of neurons in adjacent layers. Each synapse element comprises a material that applies a selected weight to signals passing between neurons connected to that synapse element.

公开(公告)号：US20170133099A1

公开(公告)日：2017-05-11

申请号：US15348869

申请日：2016-11-10

申请人： Fu-Chang Hsu

发明人： Fu-Chang Hsu

IPC分类号： G11C16/34 ,  G11C16/10 ,  H01L27/115 ,  G11C16/04

CPC分类号： G11C16/3427 ,  G11C16/04 ,  G11C16/0466 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/1157 ,  H01L28/00

摘要： A 3D NAND array with divided string architecture. In one aspect, an apparatus includes a plurality of charge storing devices connected to form a cell string. The apparatus also includes one or more internal select gates connected between selected charge storing devices in the cell string. The one or more internal select gates divide the cell string into two or more segments of charge storing devices. Selectively enabling and disabling the one or more internal select gates during programming operates to isolate one or more selected segments to reduce program-disturb to remaining segments. In another embodiment, a method is provided for programming a memory cell of a cell string having internal select gates that isolate the memory cell to reduce the effects of program-disturb. In another embodiment, multiple memory cells of a cell string having internal select gates are programmed with reduced program-disturb.

公开(公告)号：US08933500B2

公开(公告)日：2015-01-13

申请号：US13200010

申请日：2011-09-15

申请人： Peter Wung Lee ,  Fu-Chang Hsu

发明人： Peter Wung Lee ,  Fu-Chang Hsu

IPC分类号： H01L29/788 ,  H01L21/28 ,  G11C16/04 ,  G11C16/10 ,  H01L27/115 ,  H01L29/423

CPC分类号： H01L21/28273 ,  G11C16/0441 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7883

摘要： A nonvolatile memory device has a combination of FLOTOX EEPROM nonvolatile memory arrays. Each FLOTOX-based nonvolatile memory array is formed of FLOTOX-based nonvolatile memory cells that include at least one floating gate tunneling oxide transistor such that a coupling ratio of the control gate to the floating gate of the floating gate tunneling oxide transistor is from approximately 60% to approximately 70% and a coupling ratio of the floating gate to the drain region of the floating gate tunneling oxide transistor is maintained as a constant of is from approximately 10% to approximately 20% and such that a channel length of the channel region is decreased such that during the programming procedure a negative programming voltage level is applied to the control gate and a moderate positive programming voltage level is applied to the drain region to prevent the moderate positive programming voltage level from exceeding a drain-to-source breakdown voltage.

摘要翻译： 非易失性存储器件具有FLOTOX EEPROM非易失性存储器阵列的组合。 每个基于FLOTOX的非易失性存储器阵列由基于FLOTOX的非易失性存储器单元形成，其包括至少一个浮置栅极隧穿氧化物晶体管，使得控制栅极与浮置栅极隧道氧化物晶体管的浮置栅极的耦合比率约为60 ％至约70％，并且将浮置栅极与漏极区域的浮动栅极氧化物晶体管的耦合比保持为约10％至约20％的常数，并且使得沟道区的沟道长度为 减小，使得在编程过程期间将负编程电压电平施加到控制栅极，并且向漏极区域施加中等的正编程电压电平，以防止中等正编程电压电平超过漏源至源极击穿电压。

公开(公告)号：US08462553B2

公开(公告)日：2013-06-11

申请号：US12930022

申请日：2010-12-23

申请人： Peter Wung Lee ,  Fu-Chang Hsu

发明人： Peter Wung Lee ,  Fu-Chang Hsu

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C16/0433 ,  H01L27/11521

摘要： Two-transistor FLOTOX EEPROM cells are collected to form an alterable unit such as a byte. Each of the two-transistor FLOTOX EEPROM cells has a bit line connected to a drain of a select transistor of each of the two-transistor FLOTOX EEPROM cells and a source line placed in parallel with the bit line and connected to a source of a floating gate transistor of each of the two-transistor FLOTOX EEPROM cells. In a program operation, the bit lines are connected to a very large programming voltage level and the source lines are connected to a punch through inhibit voltage level. The punch through inhibit voltage level is approximately one half the very large programming voltage level. The lower drain-to-source voltage level permits the select transistor and the floating gate transistor to have smaller channel lengths and therefore a lower drain-to-source breakdown voltage.

摘要翻译： 收集双晶体管FLOTOX EEPROM单元以形成诸如字节的可变单元。 每个双晶体管FLOTOX EEPROM单元具有连接到每个双晶体管FLOTOX EEPROM单元的选择晶体管的漏极的位线和与位线并联放置并连接到浮置源的源极线 两个晶体管FLOTOX EEPROM单元的栅极晶体管。 在编程操作中，位线连接到非常大的编程电压电平，并且源极线通过禁止电压电平连接到冲头。 通过禁止电压电平的冲击大约是非常大的编程电压电平的一半。 较低的漏极 - 源极电压电平允许选择晶体管和浮动栅极晶体管具有较小的沟道长度，因此具有较低的漏极 - 源极击穿电压。

公开(公告)号：US08455923B2

公开(公告)日：2013-06-04

申请号：US13135220

申请日：2011-06-29

申请人： Peter Wung Lee ,  Han-Rei Ma ,  Fu-Chang Hsu

发明人： Peter Wung Lee ,  Han-Rei Ma ,  Fu-Chang Hsu

IPC分类号： H01L27/118

CPC分类号： H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/66825 ,  H01L29/7881

摘要： An integrated circuit formed of nonvolatile memory array circuits, logic circuits and linear analog circuits is formed on a substrate. The nonvolatile memory array circuits, the logic circuits and the linear analog circuits are separated by isolation regions formed of a shallow trench isolation. The nonvolatile memory array circuits are formed in a triple well structure. The nonvolatile memory array circuits are NAND-based NOR memory circuits formed of at least two floating gate transistors that are serially connected such that at least one of the floating gate transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. Each column of the NAND-based NOR memory circuits are associated with and connected to one bit line and one source line.

摘要翻译： 由非易失性存储器阵列电路，逻辑电路和线性模拟电路形成的集成电路形成在基板上。 非易失性存储器阵列电路，逻辑电路和线性模拟电路由通过浅沟槽隔离形成的隔离区隔开。 非易失性存储器阵列电路形成为三重阱结构。 非易失性存储器阵列电路是由至少两个串联连接的浮栅晶体管形成的基于NAND的NOR存储器电路，使得浮栅晶体管中的至少一个用作选择栅极晶体管，以防止漏电流通过电荷保持晶体管， 电荷保持晶体管不被选择用于读取。 基于NAND的NOR存储器电路的每列与一个位线和一个源极线相关联并连接到一个位线和一个源极线。

公开(公告)号：US08345481B2

公开(公告)日：2013-01-01

申请号：US13317678

申请日：2011-10-25

申请人： Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

发明人： Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/30 ,  G11C2211/5641 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  Y10T29/41

摘要： A NOR flash nonvolatile memory or reconfigurable logic device has an array of NOR flash nonvolatile memory circuits that includes charge retaining transistors serially connected in a NAND string such that at least one of the charge retaining transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. The topmost charge retaining transistor's drain is connected to a bit line parallel to the charge retaining transistors and the bottommost charge retaining transistor's source is connected to a source line and is parallel to the bit line. The charge retaining transistors are programmed and erased with a Fowler-Nordheim tunneling process.

摘要翻译： NOR闪存非易失性存储器或可重构逻辑器件具有NOR闪存非易失性存储器电路阵列，其包括串联连接在NAND串中的电荷保持晶体管，使得至少一个电荷保持晶体管用作选择栅极晶体管，以防止漏电流通过 当电荷保持晶体管未被选择用于读取时的电荷保持晶体管。 最上面的电荷保持晶体管的漏极连接到与电荷保持晶体管平行的位线，并且最下面的电荷保持晶体管的源极连接到源极线并且平行于位线。 电荷保持晶体管通过Fowler-Nordheim隧道工艺进行编程和擦除。

公开(公告)号：US08274829B2

公开(公告)日：2012-09-25

申请号：US12455936

申请日：2009-06-09

申请人： Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

发明人： Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

IPC分类号： G11C11/34 ,  G11C11/4193

CPC分类号： G11C8/12 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16

摘要： An apparatus and method for operating an array of NOR connected flash nonvolatile memory cells erases the array in increments of a page, block, sector, or the entire array while minimizing operational disturbances and providing bias operating conditions to prevent gate to source breakdown in peripheral devices. The apparatus has a row decoder circuit and a source decoder circuit for selecting the nonvolatile memory cells for providing biasing conditions for reading, programming, verifying, and erasing the selected nonvolatile memory cells while minimizing operational disturbances and preventing gate to source breakdown in peripheral devices.

摘要翻译： 用于操作NOR连接的闪存非易失性存储器单元的阵列的装置和方法以页，块，扇区或整个阵列的增量擦除阵列，同时最小化操作干扰并提供偏置操作条件以防止外围设备中的门源故障 。 该装置具有行解码器电路和源解码器电路，用于选择非易失性存储单元，以提供用于读取，编程，验证和擦除所选择的非易失性存储单元的偏置条件，同时最小化操作干扰并防止门外围设备中的故障。

公开(公告)号：US20120072647A1

公开(公告)日：2012-03-22

申请号：US13200141

申请日：2011-09-19

申请人： Peter Wung Lee ,  Fu-Chang Hsu

发明人： Peter Wung Lee ,  Fu-Chang Hsu

IPC分类号： G06F12/00 ,  H05K3/00

CPC分类号： G06F12/0638 ,  G06F12/0246 ,  G06F2212/7208 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1045 ,  G11C11/005 ,  G11C16/32 ,  G11C2216/30 ,  Y02D10/13 ,  Y10T29/49124

摘要： A semiconductor chip contains four different memory types, EEPROM, NAND Flash, NOR Flash and SRAM, and a plurality of major serial/parallel interfaces such as I2C, SPI, SDI and SQI in one memory chip. The memory chip features write-while-write and read-while-write operations as well as read-while-transfer and write-while-transfer operations. The memory chip provides for eight pins of which two are for power and up to four pins have no connection for specific interfaces and uses a novel unified nonvolatile memory design that allow the integration together of the aforementioned memory types integrated together into the same semiconductor memory chip.

摘要翻译： 半导体芯片在一个存储器芯片中包含四种不同的存储器类型，EEPROM，NAND闪存，NOR闪存和SRAM以及多个主要的串行/并行接口，例如I2C，SPI，SDI和SQI。 内存芯片具有写时同时写入和读写操作以及读写同时传输和写时同时传输操作。 存储器芯片提供八个引脚，其中两个用于供电，最多四个引脚没有连接用于特定接口，并且使用新颖的统一的非易失性存储器设计，允许集成在一起的上述存储器类型集成在同一半导体存储器芯片 。

公开(公告)号：US20110170357A1

公开(公告)日：2011-07-14

申请号：US13072281

申请日：2011-03-25

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

IPC分类号： G11C16/04

CPC分类号： H01L27/115 ,  G11C11/005 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

摘要翻译： 公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。 此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。 与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。 此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。 该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。