公开(公告)号：US20190206743A1

公开(公告)日：2019-07-04

申请号：US15860840

申请日：2018-01-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG ,  Jianwei PENG ,  Yi QI ,  Hsien-Ching LO ,  Jerome CIAVATTI ,  Ruilong XIE

IPC: H01L21/8234 ,  H01L29/08 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L21/823487 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2018 ,  H01L21/823418 ,  H01L21/823456 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method of manufacturing a vertical fin field effect transistor includes forming a first fin in a first device region of a substrate, forming a second fin in a second device region of the substrate, and forming a sacrificial gate having a first gate length adjacent to the first and second fins. After forming a block mask over the sacrificial gate within the first device region, a deposition step or an etching step is used to increase or decrease the gate length of the sacrificial gate within the second device region. Top source/drain junctions formed over the fins are self-aligned to the gate in each of the first and second device regions.

公开(公告)号：US20190198503A1

公开(公告)日：2019-06-27

申请号：US16186781

申请日：2018-11-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Manfred ELLER

IPC: H01L27/108 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/06

CPC classification number: H01L27/10826 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0629 ,  H01L27/0886 ,  H01L27/10855 ,  H01L27/10879 ,  H01L29/785

Abstract: A semiconductor memory device includes, for example, a substrate having a fin having a web portion extending from the substrate and a first overhanging fin portion extending outward from the web portion and spaced from the substrate, the fin comprising a source/drain region in the web portion of the fin, a first source/drain region in the first overhanging fin portion, an isolation material surrounding the web portion and disposed under the first overhanging fin portion of the fin, an upper surface of the isolation material being below an upper surface of the fin, a first gate disposed over the fin between the source/drain region in the web portion of the fin and the first source/drain region in the first overhanging fin portion of the fin, and a capacitor operably electrically connected to the first source/drain region in the first overhanging fin portion.

公开(公告)号：US20190067262A1

公开(公告)日：2019-02-28

申请号：US15689934

申请日：2017-08-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG ,  Randy W. MANN

IPC: H01L27/02 ,  H01L27/092 ,  H01L27/11 ,  H01L29/423 ,  H01L23/532 ,  H01L23/522 ,  H01L21/8238 ,  H01L21/768

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a SRAM structure with alternate gate pitches and methods of manufacture. The structure includes an array of memory cells having a plurality of gate structures with varying gate pitches, the varying gate pitches comprising a first dimension sized for placement of a bitline contact and a second dimension sized for placement of source/drain contacts, the first dimension being larger than the second dimension.

公开(公告)号：US20180374857A1

公开(公告)日：2018-12-27

申请号：US15634227

申请日：2017-06-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Jerome CIAVATTI

IPC: H01L27/11 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/306 ,  H01L21/311 ,  H01L21/768

Abstract: A vertical SRAM cell includes a first (1st) inverter having a 1st pull-up (PU) transistor and a 1st pull-down (PD) transistor. The 1st PU and 1st PD transistors have a bottom source/drain (S/D) region disposed on a substrate and a channel extending upwards from a top surface of the bottom S/D region. A second (2nd) inverter has a 2nd PU transistor and a 2nd PD transistor. The 2nd PU and 2nd PD transistors have a bottom S/D region disposed on the substrate and a channel extending upwards from a top surface of the bottom S/D region. A 1st metal contact is disposed on sidewalls, and not on the top surface, of the bottom S/D regions of the 1st PU and 1st PD transistors. A 2nd metal contact is disposed on sidewalls, and not on the top surface, of the bottom S/D regions of the 2nd PU and 2nd PD transistors.

公开(公告)号：US20180308759A1

公开(公告)日：2018-10-25

申请号：US15496429

申请日：2017-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Josef WATTS

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L21/28

CPC classification number: H01L21/823437 ,  H01L21/28247 ,  H01L21/31111 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/785

Abstract: A method includes providing a semiconductor structure having a substrate and a plurality of fins extending upwards from the substrate. A CT pillar layer is disposed over the semiconductor structure. A CT mask is lithographically patterned over the CT pillar layer. The CT mask is anisotropically etched to remove exposed portions of the CT pillar layer and to form a CT pillar between the fins. A dummy gate structure is disposed across the CT pillar. The dummy gate structure is replaced with first and second metal gate structures that are electrically isolated from each other by the CT pillar.

公开(公告)号：US20180197867A1

公开(公告)日：2018-07-12

申请号：US15404754

申请日：2017-01-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Manfred ELLER

IPC: H01L27/108 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/06

CPC classification number: H01L27/10826 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0629 ,  H01L27/0886 ,  H01L27/10855 ,  H01L27/10879 ,  H01L29/785

Abstract: A semiconductor memory device includes, for example, a substrate having a fin having a web portion extending from the substrate and a first overhanging fin portion extending outward from the web portion and spaced from the substrate, the fin comprising a source/drain region in the web portion of the fin, a first source/drain region in the first overhanging fin portion, an isolation material surrounding the web portion and disposed under the first overhanging fin portion of the fin, an upper surface of the isolation material being below an upper surface of the fin, a first gate disposed over the fin between the source/drain region in the web portion of the fin and the first source/drain region in the first overhanging fin portion of the fin, and a capacitor operably electrically connected to the first source/drain region in the first overhanging fin portion.

公开(公告)号：US20180138203A1

公开(公告)日：2018-05-17

申请号：US15354205

申请日：2016-11-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG ,  Min-Hwa CHI

IPC: H01L27/12 ,  H01L29/10 ,  H01L29/06 ,  H01L23/535 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/823878 ,  H01L29/1087 ,  H01L29/4983 ,  H01L29/78 ,  H01L29/78648

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to self-aligned back-plane and well contacts for a fully depleted silicon on insulator device and methods of manufacture. The structure includes a back-plane, a p-well and an n-well formed within a bulk substrate; a contact extending from each of the back-plane, the p-well and the n-well; a gate structure formed above the back-plane, the p-well and the n-well; and an insulating spacer isolating the contact of the back-plane from the gate structure.

公开(公告)号：US20170294336A1

公开(公告)日：2017-10-12

申请号：US15634091

申请日：2017-06-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Min-hwa CHI

IPC: H01L21/74 ,  H01L29/06 ,  H01L29/10 ,  H01L21/762

CPC classification number: H01L21/743 ,  H01L21/76229 ,  H01L21/7624 ,  H01L21/76283 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/481 ,  H01L29/0649 ,  H01L29/1087

Abstract: Devices and methods of fabricating integrated circuit devices for dynamically applying bias to back plates and/or p-well regions are provided. One method includes, for instance: obtaining a wafer with a silicon substrate, at least one first oxide layer, at least one silicon layer, and at least one second oxide layer; forming at least one recess in the wafer; depositing at least one third oxide layer over the wafer and filling the at least one recess; depositing a silicon nitride layer over the wafer; and forming at least one opening having sidewalls and a bottom surface within the filled at least one recess. An intermediate semiconductor device is also disclosed.

公开(公告)号：US20170294309A1

公开(公告)日：2017-10-12

申请号：US15093310

申请日：2016-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Min-hwa CHI

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234

CPC classification number: H01L21/0337 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823456

Abstract: A method includes, for example, providing a starting semiconductor structure having a plurality of material lines disposed over a hard mask, and the hard mask disposed over a patternable layer, forming a protective layer over a portion of at least one material line, the at least one protected material line and at least one unprotected material line having a same critical dimension, oxidizing the at least one unprotected material line to increase the critical dimension compared to the first critical dimension of the at least one protected material line, and etching at least a portion of the oxidized unprotected material line so that the etched critical dimension of the at least one etched material line is different from the first critical dimension of the at least one protected material line.

公开(公告)号：US20170294308A1

公开(公告)日：2017-10-12

申请号：US15093292

申请日：2016-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Min-hwa CHI

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234

CPC classification number: H01L21/0337 ,  H01L21/02238 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823475

Abstract: A method includes, for example, a starting semiconductor structure comprising a plurality of material lines disposed over a hard mask, and the hard mask disposed over a patternable layer, forming a first protective layer over some of the plurality of material lines, the protected material lines and the unprotected material lines having a same corresponding first critical dimension, oxidizing the unprotected material lines so that the oxidized unprotected material lines have an increased second critical dimension greater than the first critical dimension, removing the first protective layer, forming a second protective layer over some of the plurality of protected material lines having the first critical dimension and some of the oxidized material lines having the second critical dimension, and oxidizing the unprotected material lines so that the oxidized unprotected material lines have an increased third critical dimension greater than the first critical dimension.