公开(公告)号：US09508604B1

公开(公告)日：2016-11-29

申请号：US15142052

申请日：2016-04-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Chanro Park ,  Hoon Kim ,  Ruilong Xie

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/3115

CPC classification number: H01L21/823821 ,  H01L27/0924 ,  H01L29/6656 ,  H01L29/66803 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, forming a first plurality of fins for a type 1 device and a second plurality of fins for a type 2 device, forming a first counter-doped sidewall spacer structure adjacent the first fins, forming a second counter-doped sidewall spacer structure adjacent the second fins and a counter-doped material structure in a space between the first fins, forming a recessed layer of flowable oxide on the devices such that portions of the first and second counter-doped sidewall spacers are exposed above the flowable oxide layer, and performing a common etching process operation to remove at least a portion of the exposed portions of the first and second counter-doped sidewall spacer structures.

Abstract translation: 本文公开的一种说明性方法包括形成用于类型1装置的第一多个翅片和用于2型装置的第二多个翅片，形成与第一翅片相邻的第一反掺杂侧壁间隔结构，形成 邻近第二散热片的第二反掺杂侧壁间隔结构和在第一散热片之间的空间中的反掺杂材料结构，在器件上形成可流动氧化物的凹陷层，使得第一和第二反掺杂侧壁间隔物的部分为 暴露在可流动氧化物层之上，并执行公共蚀刻工艺操作以去除第一和第二反掺杂侧壁间隔结构的暴露部分的至少一部分。

公开(公告)号：US09502308B1

公开(公告)日：2016-11-22

申请号：US14944659

申请日：2015-11-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Hoon Kim ,  Ruilong Xie ,  Min Gyu Sung

IPC: H01L21/70 ,  H01L21/8238 ,  H01L21/768 ,  H01L27/092 ,  H01L23/535 ,  H01L23/532

CPC classification number: H01L21/823871 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924

Abstract: A method includes forming first and second contact openings so as to expose first and second source/drain regions, respectively, of a semiconductor material. At least one process operation is performed to selectively form a first liner only in the first contact opening. The first liner covers a bottom portion of the first contact opening and exposes a sidewall portion of the first contact opening. A second liner is formed in the first and second contact openings. At least one process operation is performed so as to form a conductive material above the second liner to fill the first and second contact openings and define first and second contacts conductively coupled to the first and second source/drain regions, respectively.

Abstract translation: 一种方法包括形成第一和第二接触开口以分别暴露半导体材料的第一和第二源/漏区。 执行至少一个处理操作以仅在第一接触开口中选择性地形成第一衬里。 第一衬垫覆盖第一接触开口的底部并暴露第一接触开口的侧壁部分。 第二衬垫形成在第一和第二接触开口中。 执行至少一个处理操作，以在第二衬垫上方形成导电材料，以填充第一和第二接触开口，并分别限定导电耦合到第一和第二源/漏区的第一和第二触点。

公开(公告)号：US09478661B1

公开(公告)日：2016-10-25

申请号：US14696954

申请日：2015-04-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Hoon Kim ,  Min Gyu Sung

IPC: H01L21/308 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L29/785 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/76897 ,  H01L29/6656 ,  H01L29/66795

Abstract: Semiconductor device structures having fin structure(s) and fabrication methods thereof are presented. The methods include: providing a first mask above a substrate structure and a second mask above the first mask and the substrate structure; removing portions of the first mask not underlying the second mask and selectively etching the substrate structure using the second mask to form at least one cavity therein; providing a third mask over portions of the substrate structure not underlying the second mask and removing the second mask; and selectively etching the substrate structure using remaining portions of the first mask and the third mask to the form fin structure(s) of the semiconductor device structure, where the fin structure(s) is self-aligned with the at least one cavity in the substrate structure. For example, the semiconductor device structure can be a fin-type transistor structure, and the method can include forming a source/drain region within a cavity.

Abstract translation: 提出了具有翅片结构的半导体器件结构及其制造方法。 所述方法包括：在第一掩模和衬底结构之上提供衬底结构上方的第一掩模和第二掩模; 去除第一掩模的不在第二掩模下面的部分，并使用第二掩模选择性地蚀刻衬底结构，以在其中形成至少一个空腔; 在不在所述第二掩模下方的所述衬底结构的部分上提供第三掩模并且移除所述第二掩模; 以及使用所述第一掩模和所述第三掩模的剩余部分将所述衬底结构选择性地蚀刻到所述半导体器件结构的形式鳍结构，其中所述鳍结构与所述第一掩模和所述第三掩模中的所述至少一个空腔自对准 底物结构。 例如，半导体器件结构可以是鳍式晶体管结构，并且该方法可以包括在腔内形成源极/漏极区域。

公开(公告)号：US20160181426A1

公开(公告)日：2016-06-23

申请号：US15055805

申请日：2016-02-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hoon Kim ,  Chanro Park ,  Min Gyu Sung

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/165 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: A device includes a gate structure having an axial length that is positioned above an active region of a semiconductor substrate and includes a first gate structure portion positioned above the active region and second gate structure portions positioned above an isolation region formed in the semiconductor substrate. An etch stop layer is positioned on the gate structure and covers sidewall surfaces of the second gate structure portions but does not cover any sidewall surfaces of the first gate structure portion. First and second contact trenches extend continuously along the first gate structure portion for less than the axial length of the gate structure and are positioned above at least a portion of the active region on respective opposing first and second sides of the gate structure. An epi semiconductor material is positioned on the active region within each of the first and second contact trenches.

Abstract translation: 一种器件包括具有位于半导体衬底的有源区上方的轴向长度的栅极结构，并且包括位于有源区上方的第一栅极结构部分和位于半导体衬底中形成的隔离区上方的第二栅极结构部分。 蚀刻停止层位于栅极结构上并且覆盖第二栅极结构部分的侧壁表面，但不覆盖第一栅极结构部分的任何侧壁表面。 第一和第二接触沟槽沿着第一栅极结构部分连续延伸以小于栅极结构的轴向长度，并且位于栅极结构的相对的相对的第一和第二侧上的有源区域的至少一部分上方。 外延半导体材料位于第一和第二接触沟槽的每一个内的有源区域上。

公开(公告)号：US20160133726A1

公开(公告)日：2016-05-12

申请号：US14536026

申请日：2014-11-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Ryan Ryoung-Han Kim

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/308 ,  H01L27/11

CPC classification number: H01L29/66795 ,  H01L21/3086 ,  H01L27/1104 ,  H01L29/0642 ,  H01L29/66553 ,  H01L29/6681

Abstract: One illustrative method disclosed herein includes, among other things, forming a first plurality of fins in the first region of the substrate, a second plurality of fins in the second region of the substrate, and a space in the substrate between two adjacent fins in the second region that corresponds to a first isolation region to be formed in the second region, forming a fin removal masking layer above the first and second regions of the substrate, wherein the fin removal masking layer has an opening positioned above at least a portion of at least one of the first plurality of fins, while masking all of the second plurality of fins in the second region and the space for the first isolation region, and performing an etching process through the first opening to remove the portions of the at least one of the first plurality of fins.

Abstract translation: 本文公开的一种说明性方法包括在衬底的第一区域中形成第一多个鳍片，在衬底的第二区域中形成第二多个鳍片，以及在衬底中的两个相邻鳍片之间的空间 第二区域，其对应于将形成在第二区域中的第一隔离区域，在基板的第一和第二区域上方形成散热片去除掩模层，其中散热片移除掩模层具有位于至少一部分上方的开口 在第二区域中的所有第二多个散热片和第一隔离区域的空间中遮挡所有的第一多个散热片中的至少一个，并且通过第一开口执行蚀刻处理以去除至少一个 第一组多个翅片。

公开(公告)号：US20160042954A1

公开(公告)日：2016-02-11

申请号：US14452606

申请日：2014-08-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Chanro Park ,  Hoon Kim

IPC: H01L21/28 ,  H01L29/49 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/28123 ,  H01L21/28088 ,  H01L21/32139 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Embodiments of the present invention provide a replacement metal gate and a fabrication process with reduced lithography steps. Using selective etching techniques, a layer of fill metal is used to protect the dielectric layer in the trenches, eliminating the need for some lithography steps. This, in turn, reduces the overall cost and complexity of fabrication. Furthermore, additional protection is provided during etching, which serves to improve product yield.

Abstract translation: 本发明的实施例提供了一种替代金属栅极和具有减小的光刻步骤的制造工艺。 使用选择性蚀刻技术，使用一层填充金属来保护沟槽中的电介质层，消除了对一些光刻步骤的需要。 这又降低了整体成本和制造的复杂性。 此外，在蚀刻期间提供额外的保护，其用于提高产品产率。

公开(公告)号：US20150380304A1

公开(公告)日：2015-12-31

申请号：US14314670

申请日：2014-06-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Kwanyong Lim ,  Hiroaki Niimi

IPC: H01L21/768 ,  H01L23/532 ,  H01L29/66

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/76855 ,  H01L21/76856 ,  H01L23/485 ,  H01L23/53266 ,  H01L29/41766 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Aspects of the present invention relate to approaches for forming a narrow source-drain contact in a semiconductor device. A contact trench can be etched to a source-drain region of the semiconductor device. A titanium liner can be deposited in this contact trench such that it covers substantially an entirety of the bottom and walls of the contact trench. An x-metal layer can be deposited over the titanium liner on the bottom of the contact trench. A titanium nitride liner can then be formed on the walls of the contact trench. The x-metal layer prevents the nitriding of the titanium liner on the bottom of the contact trench during the formation of the nitride liner.

Abstract translation: 本发明的方面涉及在半导体器件中形成窄源极 - 漏极接触的方法。 可以将接触沟槽蚀刻到半导体器件的源极 - 漏极区域。 可以在该接触沟槽中沉积钛衬里，使得其覆盖接触沟槽的基本上整个底部和壁。 可以在接触沟槽的底部上的钛衬垫上沉积x-金属层。 然后可以在接触沟槽的壁上形成氮化钛衬垫。 在形成氮化物衬垫期间，x-金属层防止了接触沟槽底部的钛衬里的氮化。

公开(公告)号：US10446399B2

公开(公告)日：2019-10-15

申请号：US15339497

申请日：2016-10-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Chanro Park ,  Hoon Kim

IPC: H01L21/28 ,  H01L29/66 ,  H01L27/088 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/311

Abstract: A method includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with active region(s) separated by isolation regions, the active region(s) including source/drain regions of epitaxial semiconductor material, dummy gate structures adjacent each source/drain region, the dummy gate structures including dummy gate electrodes with spacers adjacent opposite sidewalls thereof and gate caps thereover, and openings between the dummy gate structures. The method further includes filling the openings with a dielectric material, recessing the dielectric material, resulting in a filled and recessed structure, and forming a hard mask liner layer over the filled and recessed structure to protect against loss of the recessed dielectric material during subsequent removal of unwanted dummy gate electrodes. A resulting semiconductor structure formed by the method is also provided.

公开(公告)号：US10312154B2

公开(公告)日：2019-06-04

申请号：US15705888

申请日：2017-09-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Steven Bentley ,  Puneet Harischandra Suvarna ,  Chanro Park ,  Min Gyu Sung ,  Lars Liebmann ,  Su Chen Fan ,  Brent Anderson

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/84 ,  H01L21/8234

Abstract: A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a spacer layer that is formed over an endwall of the fin. The spacer layer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.

公开(公告)号：US10297597B2

公开(公告)日：2019-05-21

申请号：US15689711

申请日：2017-08-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Ruilong Xie ,  Chanro Park ,  Murat Kerem Akarvardar

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/06 ,  H01L21/02 ,  H01L21/3105

Abstract: Structures for the isolation of a fin-type field-effect transistor and methods of forming isolation for a fin-type field-effect transistor. A first dielectric layer is formed that encapsulates a plurality of fins. A second dielectric layer is formed that surrounds the first dielectric layer and the plurality of fins. A surface of the second dielectric layer relative to a surface of the first dielectric layer. A liner is conformally deposited on the surface of the first dielectric layer and on the recessed surface of the second dielectric layer. A section of the liner is removed to expose the surface of the first dielectric layer. The exposed surface of the first dielectric layer is recessed to reveal a portion of each of the plurality of fins.