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    Circuits, architectures, systems and methods for overvoltage protection
    72.
    发明授权
    Circuits, architectures, systems and methods for overvoltage protection 失效
    电路，架构，系统和过电压保护方法

    公开(公告)号：US07026839B1

    公开(公告)日：2006-04-11

    申请号：US10606907

    申请日：2003-06-26

    申请人： Lei Wu ,  Yonghua Song

    发明人： Lei Wu ,  Yonghua Song

    IPC分类号： H03K17/16

    CPC分类号： H03F1/52 ,  H01L27/0251 ,  H03F3/45475 ,  H03F2200/444 ,  H03F2203/45134 ,  H03K19/003

    摘要： Circuits, architectures, a system and methods for protecting against overvoltages in a high-speed differential signal or circuit. The circuit generally includes (a) a differential signal transmission line, (b) a common mode circuit coupled to and configured to reduce a swing of the differential signal transmission line, and (c) an overvoltage protection circuit coupled to the common mode circuit, wherein the common mode circuit is electrically interposed between the overvoltage protection circuit and the differential signal transmission line. The architectures and/or systems generally include an integrated circuit that embodies one or more of the inventive concepts disclosed herein. The method generally includes shunting the overvoltage to a ground potential through the termination circuit when the differential circuit receives the overvoltage, but otherwise processing the differential signal through circuitry coupled to the differential circuit. The present invention advantageously provides a satisfactory level of overvoltage protection for nearly all applications in which conventional CMOS circuitry can be used, while at the same time, having very little, if any, adverse effect on differential data signal transmission speed.

    摘要翻译： 电路，架构，用于在高速差分信号或电路中防止过电压的系统和方法。 电路通常包括（a）差分信号传输线，（b）共模电路，其耦合到并且被配置为减小差分信号传输线的摆动，以及（c）耦合到共模电路的过电压保护电路， 其中所述共模电路被电插入所述过电压保护电路和所述差动信号传输线之间。 架构和/或系统通常包括体现本文公开的一个或多个发明构思的集成电路。 该方法通常包括当差分电路接收到过电压时通过终端电路将过电压分流到地电位，而通过耦合到差分电路的电路处理差分信号。 本发明有利地为几乎可以使用常规CMOS电路的所有应用提供令人满意的过电压保护水平，同时对差分数据信号传输速度具有很少的（如果有的话）不利影响。

    Architectures, circuits, systems and methods for reducing latency in data communications
    74.
    发明申请
    Architectures, circuits, systems and methods for reducing latency in data communications 有权
    用于减少数据通信延迟的架构，电路，系统和方法

    公开(公告)号：US20050034009A1

    公开(公告)日：2005-02-10

    申请号：US10634218

    申请日：2003-08-04

    申请人： Pantas Sutardja ,  Lei Wu ,  Hongying Sheng

    发明人： Pantas Sutardja ,  Lei Wu ,  Hongying Sheng

    IPC分类号： G06F1/04 ,  G06F13/40

    CPC分类号： G06F13/405

    摘要： Circuits, architectures, systems and methods for facilitating data communications and/or reducing latency in data communications. The architecture includes a clock recovery loop receiving data from a host device and providing a recovered clock signal, a filter circuit receiving recovered clock signal information and providing a control signal that adjusts the transmitter clock in response to recovered clock signal information and the two clock signals, and a transmitter receiving the control signal and transmitting data to a destination device in accordance with the transmitter clock. The circuitry generally includes a clock alignment block receiving first and second periodic signals and providing a control signal in response thereto, a filter for first periodic signal information, and a logic circuit configured to combine the control signal and the filtered information, thereby providing an adjustment signal for the second periodic signal. The systems generally relate to those that include the present architecture and/or circuit. The method generally includes determining a phase difference between first and second periodic signals, one of the periodic signals being recovered from a data stream; adjusting the other periodic signal in response to the phase difference and filtered information from the recovered periodic signal; and transmitting the data stream in accordance with said adjusted periodic signal. The present invention advantageously eliminates a FIFO memory in the data path, thereby reducing transceiver latency and improving system performance.

    摘要翻译： 用于促进数据通信和/或减少数据通信中的延迟的电路，架构，系统和方法。 该架构包括时钟恢复环路，其接收来自主机设备的数据并提供恢复的时钟信号，滤波器电路接收恢复的时钟信号信息，并提供响应于恢复的时钟信号信息和两个时钟信号调整发射机时钟的控制信号 以及接收控制信号并根据发射机时钟向目的地设备发送数据的发射机。 电路通常包括时钟对准块，其接收第一和第二周期信号并响应于此提供控制信号，用于第一周期性信号信息的滤波器以及被配置为组合控制信号和滤波信息的逻辑电路，由此提供调整 信号用于第二周期信号。 系统通常涉及包括本架构和/或电路的系统。 该方法通常包括确定第一和第二周期信号之间的相位差，从数据流中恢复一个周期信号; 响应于来自恢复的周期信号的相位差和滤波信息调整另一周期信号; 以及根据所述调整的周期信号发送数据流。 本发明有利地消除数据路径中的FIFO存储器，从而减少收发机等待时间并提高系统性能。

    Apparatus and method for high throughput electrorotation analysis
    75.
    发明授权
    Apparatus and method for high throughput electrorotation analysis 有权
    用于高通量电磁分析的装置和方法

    公开(公告)号：US06448794B1

    公开(公告)日：2002-09-10

    申请号：US09643362

    申请日：2000-08-22

    申请人： Jing Cheng ,  Junquan Xu ,  Xiaoshan Zhu ,  Litian Liu ,  Xiao-Bo Wang ,  Lei Wu

    发明人： Jing Cheng ,  Junquan Xu ,  Xiaoshan Zhu ,  Litian Liu ,  Xiao-Bo Wang ,  Lei Wu

    IPC分类号： G01R2708

    CPC分类号： G01N33/48707 ,  B01J2219/00497 ,  B01J2219/00527 ,  B01J2219/00529 ,  B01J2219/00587 ,  B01J2219/00596 ,  B01J2219/00653 ,  B01J2219/00659 ,  B01J2219/00707 ,  B01J2219/0072 ,  Y10S436/806

    摘要： The present invention concerns a high throughput electrorotation chip having an array of electrorotation units and methods of use thereof. To make the high throughput electrorotation chip, a plurality of electrorotation units (EU) are fabricated on a substrate or support and each EU is capable of producing a rotating electric field upon the application of an appropriate electrical signal. Exemplary embodiments include a row-column configuration of EUs having four electrode elements realized through two conductive-layers. The electrode elements may be linear, concave, or convex. Thin plates having one or multiple holes are bound to high-throughput electrorotation chips to form assay chambers having one or multiple wells. Particles can be introduced to the wells and electrorotation measurements can be performed on the particles. The high throughput electrorotation chip and chamber may be used for cell-based screening for leading drug candidate molecules from a compound library, for high-throughput characterizing particle electric properties, and for high-throughput assaying molecular compositions of unknown solutions.

    摘要翻译： 本发明涉及一种具有电极单元阵列的高通量电选机芯及其使用方法。 为了制造高通量电选芯片，在基板或支撑件上制造多个电极单元（EU），并且每个EU在施加适当的电信号时能够产生旋转电场。 示例性实施例包括具有通过两个导电层实现的四个电极元件的EU行的列列配置。 电极元件可以是线性的，凹的或凸的。 具有一个或多个孔的薄板结合到高通量电旋转切片以形成具有一个或多个孔的测定室。 可以将颗粒引入孔中，并且可以对颗粒进行电转化测量。 高通量电刺激芯片和腔室可用于来自化合物文库的主要药物候选分子的基于细胞的筛选，用于高通量表征颗粒电性质，以及用于高通量测定未知溶液的分子组成。

    Electrothermal microactuator for large vertical displacement without tilt or lateral shift
    78.
    发明授权
    Electrothermal microactuator for large vertical displacement without tilt or lateral shift 有权
    电热微致动器用于垂直位移大，无倾斜或侧向偏移

    公开(公告)号：US08776514B2

    公开(公告)日：2014-07-15

    申请号：US12743499

    申请日：2008-12-15

    申请人： Lei Wu ,  Huikai Xie

    发明人： Lei Wu ,  Huikai Xie

    IPC分类号： F01B29/10 ,  G02B26/00

    CPC分类号： B81B3/0024 ,  B81B2201/032 ,  B81B2201/047 ,  B81B2203/053

    摘要： A microactuator for displacing a platform vertically with respect to a substrate includes a first rigid frame, a first flexible bimorph beam connecting the first frame to the substrate, a second rigid frame, a second flexible bimorph beam connecting the second frame to the first frame, and a third flexible bimorph beam connecting a platform to the second frame. Activation of the first, second, and third flexible bimorph beams allows vertical displacement of the platform with respect to the substrate, with negligible lateral shift. A microactuator assembly includes a substrate, a plurality of first rigid frames, a plurality of first flexible bimorph beams, a plurality of second rigid frames, a plurality of second flexible bimorph beams, a platform, and a plurality of third flexible bimorph beams. Activation of the first, second, and third bimorph beams allows vertical displacement of the platform with respect to the substrate, with negligible lateral shift. A further embodiment with four identical such microactuators oriented at four sides of the platform, can achieve 1D or 2D angular scanning of the mirror plate by the activation of 1 or 2 adjacent microactuators.

    摘要翻译： 用于使平台相对于衬底垂直移位的微致动器包括第一刚性框架，将第一框架连接到衬底的第一柔性双压电晶片梁，第二刚性框架，将第二框架连接到第一框架的第二柔性双压电晶片梁， 以及将平台连接到第二框架的第三柔性双压电晶片。 第一，第二和第三柔性双晶片束的激活允许平台相对于衬底的垂直位移，具有可忽略的横向偏移。 微致动器组件包括基板，多个第一刚性框架，多个第一柔性双压电晶片梁，多个第二刚性框架，多个第二柔性双压电晶片梁，平台和多个第三柔性双压电晶片。 第一，第二和第三双晶片束的激活允许平台相对于衬底的垂直位移，具有可忽略的横向偏移。 具有四个相同的这样的微致动器的另一实施例在平台的四个侧面定向，可以通过激活1或2个相邻微致动器来实现镜板的1D或2D角扫描。

    Programmable pre-emphasis circuit for serial ATA
    79.
    发明授权
    Programmable pre-emphasis circuit for serial ATA 有权
    串行ATA可编程预加重电路

    公开(公告)号：US08311064B1

    公开(公告)日：2012-11-13

    申请号：US12792247

    申请日：2010-06-02

    申请人： Lei Wu ,  Timothy Hu

    发明人： Lei Wu ,  Timothy Hu

    IPC分类号： G06F13/40 ,  H04J3/04

    CPC分类号： G06F13/4072 ,  H04L25/0292 ,  H04L25/03025

    摘要： A transmitter including an analog front end configured to receive a serial signal; a control circuit configured to generate a first gain signal and a second gain signal based on a characteristic of a serial channel; a first amplifier is configured to amplify the serial signal to generate a first amplified signal based on the first gain signal; a first delay device configured to delay the serial signal to generate a first delayed signal; a second amplifier configured to amplify the first delayed signal to generate a second amplified signal based on the second gain signal; and at least one summer is configured to sum the first amplified signal and the second amplified signal to generate an output signal. The output signal is transmitted on the serial channel.

    摘要翻译： 一种发射机，包括被配置为接收串行信号的模拟前端; 控制电路，被配置为基于串行通道的特性产生第一增益信号和第二增益信号; 第一放大器被配置为基于第一增益信号放大串行信号以产生第一放大信号; 第一延迟装置，被配置为延迟所述串行信号以产生第一延迟信号; 第二放大器，被配置为基于所述第二增益信号放大所述第一延迟信号以产生第二放大信号; 并且至少一个加法器被配置为对第一放大信号和第二放大信号求和以产生输出信号。 输出信号在串行通道上传输。

    Method, system and server for charging a prepaid account
    80.
    发明授权
    Method, system and server for charging a prepaid account 有权
    方法，系统和服务器为预付账户收费

    公开(公告)号：US08078510B2

    公开(公告)日：2011-12-13

    申请号：US12272361

    申请日：2008-11-17

    申请人： Shengping Ge ,  Lei Wu

    发明人： Shengping Ge ,  Lei Wu

    IPC分类号： G06Q40/00

    CPC分类号： H04L12/14 ,  G06Q20/102 ,  G06Q20/105 ,  G06Q20/108 ,  G06Q30/04 ,  G06Q40/00 ,  G06Q50/06 ,  H04L12/1439 ,  H04L12/1467 ,  H04L12/66

    摘要： The present invention relates to prepaid services in the communication field. A method for charging a prepaid account includes: delivering the available traffic to the NAS based on the available balance of an account shared by the user and other users in response to a successful authentication of a user's access request; and delivering the available traffic to the NAS based on the available balance of the account shared by the user and other users in response to a receipt of an Accounting-Request-Interim message from the NAS. The solution provided by the invention may deliver the available traffic to a user every accounting period so that an account can be used by multiple users concurrently, whereas overdraft does not occur. The present invention also provides a system and an AAA server for charging a prepaid account.

    摘要翻译： 本发明涉及通信领域中的预付费业务。 一种对预付帐户进行计费的方法，包括：根据用户和访问请求的成功验证，基于用户和其他用户共享的帐户的可用余额，向NAS提供可用流量; 并且根据用户和其他用户共享的帐户的可用余额，响应于从NAS接收到计费请求中期消息，将可用流量传送到NAS。 本发明提供的解决方案可以在每个会计期间向用户递送可用流量，从而可以同时使用多个用户的帐户，而不会发生透支。 本发明还提供一种用于对预付帐户进行计费的系统和AAA服务器。