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96 条记录 (耗时 0.027 秒)

    Chip package structure
    71.
    发明申请
    Chip package structure 有权
    芯片封装结构

    公开(公告)号：US20070045835A1

    公开(公告)日：2007-03-01

    申请号：US11217978

    申请日：2005-08-31

    申请人： Chun-Hung Lin ,  Geng-Shin Shen

    发明人： Chun-Hung Lin ,  Geng-Shin Shen

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/3114 ,  H01L23/13 ,  H01L23/36 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

    摘要： A chip package structure includes a substrate, a chip, a first B-stage adhesive, bonding wires, a heat sink and a molding compound. The substrate comprises a first surface, a second surface and a through hole. The chip is arranged on the first surface of the substrate and electrically connected thereto while the through hole of the substrate exposes a portion of the chip. The first B-stage adhesive is arranged between the chip and the first surface of the substrate, and the chip is attached to the substrate through the first B-stage adhesive. The bonding wires are connected between the chip exposed by the through hole and second surface of the substrate. The heat sink is arranged on the first surface of the substrate, covering the chip. The molding compound is arranged on the second surface of the substrate, covering a portion of the substrate and bonding wires.

    摘要翻译： 芯片封装结构包括基板，芯片，第一B阶粘合剂，接合线，散热片和模塑料。 基板包括第一表面，第二表面和通孔。 芯片布置在基板的第一表面上并与之电连接，同时基板的通孔暴露芯片的一部分。 第一B级粘合剂布置在芯片和基板的第一表面之间，并且芯片通过第一B级粘合剂附接到基板。 接合线连接在由通孔暴露的芯片和基板的第二表面之间。 散热器布置在基板的第一表面上，覆盖芯片。 模塑料配置在基板的第二表面上，覆盖基板的一部分和接合线。

    Chip package with asymmetric molding
    72.
    发明申请
    Chip package with asymmetric molding 有权
    芯片封装，不对称成型

    公开(公告)号：US20070023872A1

    公开(公告)日：2007-02-01

    申请号：US11351651

    申请日：2006-02-10

    申请人： Geng-Shin Shen

    发明人： Geng-Shin Shen

    IPC分类号： H01L23/495

    CPC分类号： H01L23/3107 ,  H01L23/4951 ,  H01L23/49551 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

    摘要： A chip package with asymmetric molding including a lead frame, a chip, an adhesive layer, bonding wires and an encapsulant, is provided. The lead frame includes a frame body and at least a turbulent plate. The frame body has inner lead portions and outer lead portions. The turbulent plate is bended upwards to form a bulge portion and the first end of the turbulent plate is connected to the frame body. The chip is fixed under the inner lead portions and the turbulent plate is located at one side of the chip. The adhesive layer is disposed between the chip and the inner lead portions, and the bonding wires are electrically connected between the chip and the corresponding inner lead portions, respectively. The encapsulant encapsulates at least the chip, the bonding wires, the inner lead portions, the adhesive layer and the turbulent plate.

    摘要翻译： 提供具有不对称模制的芯片封装，包括引线框架，芯片，粘合剂层，接合线和密封剂。 引线框架包括框架体和至少湍流板。 框体具有内引线部和外引线部。 湍流板向上弯曲以形成凸起部分，并且湍流板的第一端连接到框架体。 芯片固定在内引线部分下方，湍流板位于芯片的一侧。 粘合剂层设置在芯片和内部引线部分之间，并且接合线分别电连接在芯片和对应的内部引线部分之间。 密封剂至少封装芯片，接合线，内引线部分，粘合剂层和湍流板。

    Flexible substrate for package
    73.
    发明申请
    Flexible substrate for package 审中-公开
    柔性基底包装

    公开(公告)号：US20060145315A1

    公开(公告)日：2006-07-06

    申请号：US11250989

    申请日：2005-10-13

    申请人： Hung-Che Shen ,  Hung-Hsin Liu ,  Geng-Shin Shen

    发明人： Hung-Che Shen ,  Hung-Hsin Liu ,  Geng-Shin Shen

    IPC分类号： H01L23/495

    CPC分类号： H01L23/3157 ,  H01L23/49572 ,  H01L24/50 ,  H01L24/86 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2224/0401

    摘要： The invention provides a flexible substrate for package of a semiconductor die. The flexible substrate includes a flexible insulating film, a plurality of first leads substantially formed on the flexible insulating film, and at least one loop-shaped second lead substantially formed on the flexible insulating film. The at least one second lead is partially disposed at a corner of a device hole of the flexible film, and is designed as being capable of preventing from fracture induced during the package of the semiconductor die. Preferably, the portion of each of the at least one second lead, to be overlapped over the semiconductor die, exhibits an L-shape, a U-shape or a Y-shape.

    摘要翻译： 本发明提供一种用于半导体管芯封装的柔性衬底。 柔性基板包括柔性绝缘膜，基本上形成在柔性绝缘膜上的多个第一引线以及基本形成在柔性绝缘膜上的至少一个环形第二引线。 所述至少一个第二引线部分地设置在所述柔性膜的器件孔的角部，并且被设计为能够防止在所述半导体管芯的封装期间引起的断裂。 优选地，要重叠在半导体管芯上的至少一个第二引线中的每一个的部分呈现L形，U形或Y形。

    Automatic creative proposal generating and filtering system and manufacturing method thereof and multiple components combining method
    77.
    发明授权
    Automatic creative proposal generating and filtering system and manufacturing method thereof and multiple components combining method 失效
    自动创意提案生成和过滤系统及其制作方法及多部件组合方法

    公开(公告)号：US08245193B2

    公开(公告)日：2012-08-14

    申请号：US12119545

    申请日：2008-05-13

    申请人： Chun-Fang Cheng ,  Geng-Shin Shen ,  Hui-Chung Che ,  Hou-Bai Lee

    发明人： Chun-Fang Cheng ,  Geng-Shin Shen ,  Hui-Chung Che ,  Hou-Bai Lee

    IPC分类号： G06F9/44

    CPC分类号： G06F17/30011 ,  G06F2216/11

    摘要： The present invention discloses an automatic method and system for generating and filtering out the innovation proposals. Particularly, it is about a system, which generates all the possible element code sets, compares them to the code sets of existing objects or documents, and then filters out the novel element code sets. The system comprises a standard element depository, a permutation and combination module, a testing object processing module, a matching module, a sifting module, and an output module.

    摘要翻译： 本发明公开了一种用于生成和过滤创新提案的自动方法和系统。 特别地，它是关于一个系统，其生成所有可能的元素代码集，将它们与现有对象或文档的代码集进行比较，然后过滤掉新颖的元素代码集。 该系统包括标准元件存储器，置换和组合模块，测试对象处理模块，匹配模块，筛选模块和输出模块。

    Method for fabricating multi-chip stacked package
    78.
    发明授权
    Method for fabricating multi-chip stacked package 有权
    制造多芯片堆叠封装的方法

    公开(公告)号：US07919358B2

    公开(公告)日：2011-04-05

    申请号：US12134336

    申请日：2008-06-06

    申请人： Geng-Shin Shen ,  Yu-Ren Chen

    发明人： Geng-Shin Shen ,  Yu-Ren Chen

    IPC分类号： H01L21/00

    CPC分类号： H01L23/49575 ,  H01L23/4951 ,  H01L23/49513 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012

    摘要： A multi-chips stacked package method which includes providing a lead frame includes a top surface and a reverse surface formed by a plurality of inner leads and a plurality of outer leads; fixing a first chip on the reverse surface of the lead frame and the active surface of the first chip includes a plurality of first pads closed to the central region; forming a plurality of first metal wires, and the first pads are electrically connected to the first inner leads and the second inner leads by the first metal wires; forming a plurality of metal spacers on the thermal fin of the lead frame; fixing a second chip to electrically connect to the top surface of the first inner leads and the second inner leads; forming a plurality of second metal wires, and the second pads are electrically connected to the top surface of the first inner leads and the second inner leads; and flowing a molding to form an encapsulated material to cover the first chip, the first metal wires, the second chip, the second metal wires, the first inner leads and the second inner leads and the outer leads being exposed.

    摘要翻译： 包括提供引线框架的多芯片堆叠封装方法包括由多个内引线和多个外引线形成的顶表面和反面; 将第一芯片固定在引线框架的相反表面上，并且第一芯片的有效表面包括多个靠近中心区域的第一焊盘; 形成多个第一金属线，并且所述第一焊盘通过所述第一金属线电连接到所述第一内引线和所述第二内引线; 在引线框架的散热片上形成多个金属间隔物; 固定第二芯片以电连接到第一内引线和第二内引线的顶表面; 形成多个第二金属线，并且所述第二焊盘电连接到所述第一内引线和所述第二内引线的顶表面; 并且使模制件流动以形成覆盖第一芯片的封装材料，第一金属线，第二芯片，第二金属线，第一内引线和第二内引线以及外引线露出。