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107 条记录 (耗时 0.022 秒)

    Atomic layer deposition apparatus and method
    73.
    发明申请
    Atomic layer deposition apparatus and method 失效

    公开(公告)号：US20050142890A1

    公开(公告)日：2005-06-30

    申请号：US11055487

    申请日：2005-02-11

    申请人： Trung Doan ,  Gurtej Sandhu

    发明人： Trung Doan ,  Gurtej Sandhu

    IPC分类号： C23C16/44 ,  C23C16/455 ,  C30B25/02 ,  H01L21/00 ,  H01L21/31

    CPC分类号： C23C16/45544 ,  C23C16/4412 ,  C30B25/02 ,  H01L21/67017

    摘要： An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first deposition precursor is fed to the chamber under first vacuum conditions effective to form a first monolayer on the substrate. The first vacuum conditions are maintained at least in part by a first non-roughing vacuum pump connected to the chamber and through which at least some of the first deposition precursor flows. After forming the first monolayer, a purge gas is fed to the chamber under second vacuum conditions maintained at least in part by a second non-roughing vacuum pump connected to the chamber which is different from the first non-roughing vacuum pump and through which at least some of the purge gas flows. An atomic layer deposition apparatus is disclosed.

    Methods for preparing samples for atom probe analysis
    75.
    发明申请
    Methods for preparing samples for atom probe analysis 失效

    公开(公告)号：US20050082475A1

    公开(公告)日：2005-04-21

    申请号：US10687111

    申请日：2003-10-15

    申请人： Trung Doan

    发明人： Trung Doan

    IPC分类号： B23K26/36 ,  G01N1/04 ,  G01N1/32 ,  G01Q30/04 ,  G01Q60/00 ,  H01J49/16 ,  G01N1/28

    CPC分类号： H01J49/164 ,  B23K26/364 ,  G01N1/32 ,  G01N2001/045

    摘要： The present disclosure provides methods for preparing samples for atom probe analysis and methods for analyzing such samples. In one exemplary implementation, a surface of the sample may be positioned with respect to a laser source and laser energy may be directed from the laser source toward the sample surface, removing material from the sample to define an annulus about a sample column. The sample column may be provided with a reduced-diameter apex at its outward end, e.g., by etching. This apex may be juxtaposed with an electrode of an atom probe and material may be selectively removed from the apex for analysis by controlling energy delivered to the apex, e.g., by the electrode.

    Processes for treating a substrate and removing resist from a substrate
    76.
    发明申请
    Processes for treating a substrate and removing resist from a substrate 审中-公开
    用于处理基底并从基底去除抗蚀剂的方法

    公开(公告)号：US20050079451A1

    公开(公告)日：2005-04-14

    申请号：US10683207

    申请日：2003-10-09

    申请人： Trung Doan ,  Terry Gilton

    发明人： Trung Doan ,  Terry Gilton

    IPC分类号： G03F7/00 ,  G03F7/32 ,  G03F7/36

    CPC分类号： G03F7/322 ,  G03F7/36

    摘要： The invention includes a process whereby a solvent is utilized to remove soluble portions of a resist, and subsequently the solvent can be removed with a gas-fortified liquid. In particular aspects, the gas-fortified liquid emits bubbles during the removal of the solvent. Additionally, the gas-fortified liquid can be utilized to remove residual resist scum, and in such aspects the gas-fortified liquid can emit bubbles during the scum removal.

    摘要翻译： 本发明包括使用溶剂去除抗蚀剂的可溶部分的方法，随后用气体强化液体除去溶剂。 在特定方面，气体强化液体在除去溶剂期间会发出气泡。 此外，气体强化液体可用于去除残留的抗蚀剂浮渣，并且在这些方面，气体强化液体可以在浮渣期间发出气泡。

    Methods and apparatus for processing microfeature workpieces, e.g., for depositing materials on microfeature workpieces
    77.
    发明申请
    Methods and apparatus for processing microfeature workpieces, e.g., for depositing materials on microfeature workpieces 失效
    用于加工微型工件的方法和装置，例如用于在微型工件上沉积材料

    公开(公告)号：US20050045102A1

    公开(公告)日：2005-03-03

    申请号：US10652461

    申请日：2003-08-28

    申请人： Lingyi Zheng ,  Trung Doan ,  Lyle Breiner ,  Er-Xuan Ping ,  Kevin Beaman ,  Ronald Weimer ,  David Kubista ,  Cem Basceri

    发明人： Lingyi Zheng ,  Trung Doan ,  Lyle Breiner ,  Er-Xuan Ping ,  Kevin Beaman ,  Ronald Weimer ,  David Kubista ,  Cem Basceri

    IPC分类号： C23C16/44 ,  C23C16/455 ,  C23C16/458 ,  C23C16/00

    CPC分类号： C23C16/45546 ,  C23C16/45578 ,  C23C16/4583

    摘要： The present disclosure suggests several systems and methods for batch processing of microfeature workpieces, e.g., semiconductor wafers or the like. One exemplary implementation provides a method of depositing a reaction product on each of a batch of workpieces positioned in a process chamber in a spaced-apart relationship. A first gas may be delivered to an elongate first delivery conduit that includes a plurality of outlets spaced along a length of the conduit. A first gas flow may be directed by the outlets to flow into at least one of the process spaces between adjacent workpieces along a first vector that is transverse to the direction in which the workpieces are spaced. A second gas may be delivered to an elongate second delivery conduit that also has outlets spaced along its length. A second gas flow of the second gas may be directed by the outlets to flow into the process spaces along a second vector that is transverse to the first direction.

    摘要翻译： 本公开提出了用于批量处理微特征工件（例如半导体晶片等）的几种系统和方法。 一个示例性实施方案提供了一种在间隔开的关系中将反应产物沉积在处理室中的一批工件的每一个上的方法。 第一气体可以被输送到细长的第一输送管道，该第一输送管道包括沿管道的长度间隔开的多个出口。 第一气流可以由出口引导，沿着横向于工件间隔开的方向的第一向量流入相邻工件之间的至少一个工艺空间。 第二气体可以被输送到细长的第二输送管道，该第二输送管道也具有沿其长度间隔开的出口。 第二气体的第二气流可以由出口引导，沿着横向于第一方向的第二向量流入处理空间。

    Method for an integrated circuit contact
    79.
    发明申请
    Method for an integrated circuit contact 失效
    集成电路接触方法

    公开(公告)号：US20050020049A1

    公开(公告)日：2005-01-27

    申请号：US10923242

    申请日：2004-08-19

    申请人： Charles Dennison ,  Trung Doan

    发明人： Charles Dennison ,  Trung Doan

    IPC分类号： H01L21/768 ,  H01L21/44

    CPC分类号： H01L21/31144 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76829 ,  Y10S438/95 ,  Y10S438/97

    摘要： A process for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process including forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated during the formation of multi-level metal integrated circuits.

    摘要翻译： 在集成电路和器件的制造中形成垂直触点的工艺。 该过程消除了对精确掩模对准的需要，并允许独立于互连槽的蚀刻来控制接触孔的蚀刻。 该方法包括在衬底的表面上形成绝缘层; 在绝缘层的表面上形成蚀刻停止层; 在蚀刻停止层中形成开口; 蚀刻到穿过蚀刻停止层中的开口的第一深度并进入绝缘层以形成互连槽; 在蚀刻停止层和槽中的表面上形成光致抗蚀剂掩模; 并且继续蚀刻通过绝缘层直到到达衬底的表面以形成接触孔。 在形成多级金属集成电路期间可以重复上述过程。

    Etch process for aligning a capacitor structure and an adjacent contact corridor
    80.
    发明授权
    Etch process for aligning a capacitor structure and an adjacent contact corridor 失效
    用于对齐电容器结构和相邻触点走廊的蚀刻工艺

    公开(公告)号：US5866453A

    公开(公告)日：1999-02-02

    申请号：US527924

    申请日：1995-09-14

    申请人： Kirk D. Prall ,  Pierre Fazan ,  Trung Doan ,  Tyler Lowrey

    发明人： Kirk D. Prall ,  Pierre Fazan ,  Trung Doan ,  Tyler Lowrey

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/20

    CPC分类号： H01L27/10852 ,  H01L27/10808

    摘要： An etch process for increasing the alignment tolerances between capacitor components and an adjacent contact corridor in Dynamic Random Access Memories. The etch process is implemented in a capacitor structure formed over a semiconductor substrate. The capacitor structure includes a first conductor, a dielectric layer on the first conductor and a second conductor on the dielectric layer. The second conductor has a horizontal region laterally adjacent to and extending away from the first conductor. The etch process comprises the steps of: (a) forming a layer of patterned photoresist over the second conductor, the photoresist being patterned to expose a portion of the horizontal region of the second conductor at a desired location of a contact corridor above a source/drain region in the substrate; (b) using the photoresist as an etch mask, anisotropically etching away the exposed portions of the horizontal region of the second conductor; and (c) using the photoresist again as an etch mask, isotropically etching away substantially all of the remaining portions of the horizontal region of the second conductor and thereby enlarging the area available for locating the contact corridor. Alternatively, the horizontal region of the second conductor is removed using a single isotropic etch.

    摘要翻译： 用于增加动态随机存取存储器中电容器组件与相邻触点走廊之间的对准公差的蚀刻工艺。 蚀刻工艺在半导体衬底上形成的电容器结构中实现。 电容器结构包括第一导体，第一导体上的电介质层和电介质层上的第二导体。 第二导体具有横向邻近并远离第一导体延伸的水平区域。 蚀刻工艺包括以下步骤：（a）在第二导体上形成图案化光致抗蚀剂层，光刻胶被图案化以在第二导体的水平区域的一个源/ 漏极区域; （b）使用光致抗蚀剂作为蚀刻掩模，各向异性地蚀刻掉第二导体的水平区域的暴露部分; 和（c）再次使用光致抗蚀剂作为蚀刻掩模，各向同性地蚀刻掉第二导体的水平区域的基本上所有其余部分，从而扩大可用于定位接触走廊的面积。 或者，使用单个各向同性蚀刻去除第二导体的水平区域。