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    REFRACTORY METAL-BASED ELECTRODES FOR WORK FUNCTION SETTING IN SEMICONDUCTOR DEVICES
    71.
    发明申请
    REFRACTORY METAL-BASED ELECTRODES FOR WORK FUNCTION SETTING IN SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20060273414A1

    公开(公告)日：2006-12-07

    申请号：US11465219

    申请日：2006-08-17

    申请人： Luigi Colombo ,  James Chambers ,  Mark Visokay

    发明人： Luigi Colombo ,  James Chambers ,  Mark Visokay

    IPC分类号： H01L29/94

    CPC分类号： H01L21/823842 ,  H01L29/4958

    摘要： The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).

    Semiconductor CMOS devices and methods with NMOS high-k dielectric formed prior to core PMOS dielectric formation
    72.
    发明申请
    Semiconductor CMOS devices and methods with NMOS high-k dielectric formed prior to core PMOS dielectric formation 有权
    半导体CMOS器件和方法，在核心PMOS电介质形成之前形成NMOS高k电介质

    公开(公告)号：US20060246716A1

    公开(公告)日：2006-11-02

    申请号：US11118237

    申请日：2005-04-29

    申请人： Luigi Colombo ,  James Chambers ,  Mark Visokay

    发明人： Luigi Colombo ,  James Chambers ,  Mark Visokay

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/823857 ,  H01L27/11

    摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. A first oxide layer is formed in core and I/O regions of a semiconductor device (506). The first oxide layer is removed (508) from the core region of the device. A high-k dielectric layer is formed (510) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions of the core and I/O regions. A second oxide layer is formed (516) within NMOS regions of the core and I/O regions and a nitridation process is performed (518) that nitrides the second oxide layer and the high-k dielectric layer.

    摘要翻译： 本发明通过提供在NMOS区内选择性地形成高k电介质层的制造方法来促进半导体制造。 在半导体器件（506）的芯和I / O区域中形成第一氧化物层。 第一氧化物层从器件的核心区域移除（508）。 在芯和I / O区域上形成高k电介质层（510）。 然后，从芯和I / O区域的PMOS区域去除高k电介质层（512）。 在芯和I / O区域的NMOS区域内形成第二氧化物层（516），并且执行氮化处理（518），其氮化第二氧化物层和高k电介质层。

    MOS Transistor Gates with Doped Silicide and Methods for Making the Same
    73.
    发明申请
    MOS Transistor Gates with Doped Silicide and Methods for Making the Same 审中-公开
    具有掺杂硅化物的MOS晶体管门和制造相同的方法

    公开(公告)号：US20060244045A1

    公开(公告)日：2006-11-02

    申请号：US11457203

    申请日：2006-07-13

    申请人： Mark Visokay ,  Luigi Colombo

    发明人： Mark Visokay ,  Luigi Colombo

    IPC分类号： H01L29/788

    CPC分类号： H01L21/823842 ,  H01L21/823835

    摘要： Semiconductor devices and fabrication methods are presented, in which transistor gate structures are created using doped metal silicide materials. Upper and lower metal silicides are formed above a gate dielectric, wherein the lower metal silicide is doped with n-type impurities for NMOS gates and with p-type impurities for PMOS gates, and wherein a silicon may, but need not be formed between the upper and lower metal silicides. The lower metal silicide can be deposited directly, or may be formed through reaction of deposited metal and poly-silicon, and the lower silicide can be doped by diffusion or implantation, before or after gate patterning.

    摘要翻译： 提出了半导体器件和制造方法，其中使用掺杂的金属硅化物材料制造晶体管栅极结构。 上和下金属硅化物形成在栅极电介质上方，其中下部金属硅化物掺杂用于NMOS栅极的n型杂质和用于PMOS栅极的p型杂质，并且其中硅可以但不必形成在 上下金属硅化物。 可以直接沉积下金属硅化物，或者可以通过沉积的金属和多晶硅的反应形成下部金属硅化物，并且可以在栅极图案化之前或之后通过扩散或注入掺杂下硅化物。

    Gate stack and gate stack etch sequence for metal gate integration
    75.
    发明申请
    Gate stack and gate stack etch sequence for metal gate integration 有权
    门堆叠和门堆叠蚀刻序列用于金属栅极集成

    公开(公告)号：US20050269672A1

    公开(公告)日：2005-12-08

    申请号：US10860086

    申请日：2004-06-02

    申请人： Mark Visokay

    发明人： Mark Visokay

    IPC分类号： H01L21/28 ,  H01L21/3213 ,  H01L21/469 ,  H01L23/58

    CPC分类号： H01L21/32139 ,  H01L21/28123

    摘要： The present invention provides, in one embodiment, a process for fabricating a metal gate stack (200) for a semiconductor device (205). The process includes depositing a metal layer (210) over a gate dielectric layer (215) located over a semiconductor substrate (220). The process further includes forming a polysilicon layer (225) over the metal layer (210) and creating a protective layer (230) over the polysilicon layer (225). The process also includes placing an inorganic anti-reflective coating (235) over the protective layer (230). Other embodiments include a metal gate stack precursor structure (100) and a method of manufacturing an integrated circuit (300).

    摘要翻译： 本发明在一个实施例中提供一种用于制造用于半导体器件（205）的金属栅叠层（200）的工艺。 该方法包括在位于半导体衬底（220）上方的栅极电介质层（215）上沉积金属层（210）。 该工艺还包括在金属层（210）之上形成多晶硅层（225），并在多晶硅层（225）上形成保护层（230）。 该方法还包括将无机抗反射涂层（235）放置在保护层（230）上。 其他实施例包括金属栅极堆叠前体结构（100）和制造集成电路（300）的方法。

    MOS transistor gates with thin lower metal silicide and methods for making the same
    78.
    发明申请
    MOS transistor gates with thin lower metal silicide and methods for making the same 有权
    具有薄的下金属硅化物的MOS晶体管栅极及其制造方法

    公开(公告)号：US20050136605A1

    公开(公告)日：2005-06-23

    申请号：US10745454

    申请日：2003-12-22

    申请人： Robert Murto ,  Luigi Colombo ,  Mark Visokay

    发明人： Robert Murto ,  Luigi Colombo ,  Mark Visokay

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/44

    CPC分类号： H01L29/4975 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/6659

    摘要： Methods are presented for fabricating transistor gate structures, wherein upper and lower metal suicides are formed above a gate dielectric. In one example, the lower silicide is formed by depositing a thin first silicon-containing material over the gate dielectric, which is implanted and then reacted with a first metal by annealing to form the lower silicide. A capping layer can be formed over the first metal prior to annealing, to prevent oxidation of the metal prior to silicidation, and a barrier layer can be formed over the lower silicide to prevent reaction with subsequently formed silicon material. In another example, the lower silicide is a multilayer silicide structure including a plurality of metal silicide sublayers.

    摘要翻译： 呈现用于制造晶体管栅极结构的方法，其中上和下金属硅化物形成在栅极电介质上方。 在一个示例中，下硅化物通过在栅极电介质上沉积薄的第一含硅材料而形成，其被注入，然后通过退火与第一金属反应以形成下硅化物。 在退火之前可以在第一金属上形成覆盖层，以防止在硅化物之前金属的氧化，并且可以在下硅化物上形成阻挡层以防止随后形成的硅材料的反应。 在另一个实例中，下硅化物是包括多个金属硅化物层的多层硅化物结构。