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131 条记录 (耗时 0.039 秒)

    Storage capable of cache assignment modification
    72.
    发明申请
    Storage capable of cache assignment modification 有权
    存储能够进行缓存分配修改

    公开(公告)号：US20050216659A1

    公开(公告)日：2005-09-29

    申请号：US10863426

    申请日：2004-06-07

    申请人： Junji Ogawa ,  Naoto Matsunami ,  Akira Nishimoto ,  Yoichi Mizuno

    发明人： Junji Ogawa ,  Naoto Matsunami ,  Akira Nishimoto ,  Yoichi Mizuno

    IPC分类号： G06F3/06 ,  G06F12/00 ,  G06F12/08

    CPC分类号： G06F12/0866

    摘要： To provide a storage system which enables usage of a greater volume of cache than that of a cache memory provided to a disk array control unit, including a first disk array control unit, a second disk array control unit, a plurality of disks, and a disk array control unit communication path between a first data transfer control unit and a second data transfer control unit, wherein the first data transfer control unit selectively sets either a first path through a first host input/output control unit, the first data transfer control unit, and a first disk input/output control unit, or a second path through the first host input/output control unit, the first data transfer control unit, the disk array control unit communication path, the second data transfer control unit, and a second disk input/output control unit, and then processes a data input/output request from a host

    摘要翻译： 提供一种存储系统，其使得能够使用比提供给磁盘阵列控制单元的高速缓冲存储器更大的高速缓冲存储系统，包括第一磁盘阵列控制单元，第二磁盘阵列控制单元，多个磁盘和 第一数据传送控制单元和第二数据传送控制单元之间的盘阵列控制单元通信路径，其中第一数据传送控制单元选择性地设置通过第一主机输入/输出控制单元的第一路径，第一数据传送控制单元 以及第一盘输入/输出控制单元，或通过第一主机输入/输出控制单元的第二路径，第一数据传送控制单元，盘阵列控制单元通信路径，第二数据传输控制单元和第二 磁盘输入/输出控制单元，然后处理来自主机的数据输入/输出请求

    Semiconductor device
    73.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06166992A

    公开(公告)日：2000-12-26

    申请号：US517338

    申请日：2000-03-02

    申请人： Yoshihiro Takemae ,  Masao Taguchi ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Takaaki Suzuki ,  Junji Ogawa ,  Atsushi Hatakeyama ,  Hirohiko Mochizuki ,  Hideaki Kawai

    发明人： Yoshihiro Takemae ,  Masao Taguchi ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Takaaki Suzuki ,  Junji Ogawa ,  Atsushi Hatakeyama ,  Hirohiko Mochizuki ,  Hideaki Kawai

    IPC分类号： G06F1/04 ,  G11C7/22 ,  H01L27/02 ,  H03K3/356 ,  H03K5/13 ,  H03K5/1534 ,  H03K5/24 ,  G11C8/00

    CPC分类号： G06F1/04 ,  G11C7/22 ,  G11C7/222 ,  H03K3/356113 ,  H03K3/356156 ,  H03K5/133 ,  H03K5/1534 ,  H03K5/249

    摘要： A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle-time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has a rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.

    摘要翻译： 一种半导体器件包括：单触发脉冲发生电路，其在第一时钟信号的上升或下降定时产生具有预定脉冲宽度的单触发脉冲;周期时间测量电路，其测量第一时钟的周期时间 来自单触发脉冲发生电路输出的单触发脉冲的信号;内部时钟发生电路，其基于由周期时间测量电路测量的周期时间和从一个脉冲发生电路输出的单次脉冲产生第二时钟信号 -shot脉冲发生电路。 第二时钟信号具有与第一时钟信号相同的周期时间，并且具有比第一时钟信号高一个特定时间的上升或下降定时，并且通过减去第一时钟信号的周期时间来获得特定时间 时钟信号;以及数据输出电路，其在从第二时钟信号的上升或下降定时之后的预定延迟时间之后输出数据。

    Semiconductor device
    74.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US6009039A

    公开(公告)日：1999-12-28

    申请号：US14976

    申请日：1998-01-28

    申请人： Yoshihiro Takemae ,  Masao Taguchi ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Takaaki Suzuki ,  Junji Ogawa ,  Atsushi Hatakeyama ,  Hirohiko Mochizuki ,  Hideaki Kawai

    发明人： Yoshihiro Takemae ,  Masao Taguchi ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Takaaki Suzuki ,  Junji Ogawa ,  Atsushi Hatakeyama ,  Hirohiko Mochizuki ,  Hideaki Kawai

    IPC分类号： G06F1/04 ,  G11C7/22 ,  H03K3/356 ,  H03K5/13 ,  H03K5/1534 ,  H03K5/24 ,  G11C8/00 ,  G11C16/04

    CPC分类号： G11C7/222 ,  G06F1/04 ,  G11C7/22 ,  H03K3/356113 ,  H03K3/356156 ,  H03K5/133 ,  H03K5/1534 ,  H03K5/249 ,  G11C7/04

    摘要： A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has a rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.

    摘要翻译： 一种半导体器件包括：单脉冲发生电路，其在第一时钟信号的上升或下降定时产生具有预定脉冲宽度的单触发脉冲;周期时间测量电路，其测量第一时钟信号的周期时间 根据来自单触发脉冲发生电路的单触发脉冲输出，内部时钟发生电路，其基于由循环时间测量电路测量的周期时间和从单次脉冲发生电路输出的单次脉冲产生第二时钟信号; 射击脉冲发生电路。 第二时钟信号具有与第一时钟信号相同的周期时间，并且具有比第一时钟信号高一个特定时间的上升或下降定时，并且通过减去第一时钟信号的周期时间来获得特定时间 时钟信号;以及数据输出电路，其在从第二时钟信号的上升或下降定时之后的预定延迟时间之后输出数据。

    Semiconductor memory device capable of multidirection data access
    75.
    发明授权
    Semiconductor memory device capable of multidirection data access 失效
    能够进行多方向数据访问的半导体存储器件

    公开(公告)号：US5379264A

    公开(公告)日：1995-01-03

    申请号：US214161

    申请日：1994-03-17

    申请人： Kazuya Kobayashi ,  Kiyoshi Miyasaka ,  Junji Ogawa

    发明人： Kazuya Kobayashi ,  Kiyoshi Miyasaka ,  Junji Ogawa

    IPC分类号： G11C7/10 ,  G11C8/12 ,  G11C8/00 ,  G06F12/00 ,  G09G1/02 ,  G11C7/00

    CPC分类号： G11C8/12 ,  G11C7/1006

    摘要： A semiconductor memory device enables multi-direction data access at a high speed with a simple circuit construction. The semiconductor memory device includes a plurality of word lines, a plurality of bit lines and a plurality of memory cells connected to the bit lines and word lines. A row decoder, connected to the word lines, selects one of the word lines in response to a row address signal. A selection circuit includes a plurality of column decoders and a direction decoder. Each column decoder receives a portion of a column address signal and the direction decoder selects one of three directions in response to a direction address signal. Each column decoder is selectively enabled based upon the direction address signal. Output circuitry outputs data read out from bit lines selected by the enabled column decoders. Thus, three-dimensional bit map data can be stored in two dimensions.

    摘要翻译： 半导体存储器件能够以简单的电路结构高速地进行多方向数据存取。 半导体存储器件包括多个字线，多个位线和连接到位线和字线的多个存储器单元。 连接到字线的行解码器响应于行地址信号选择字线之一。 选择电路包括多个列解码器和方向解码器。 每列解码器接收列地址信号的一部分，并且方向解码器响应于方向地址信号选择三个方向之一。 基于方向地址信号来选择性地使能每一列解码器。 输出电路输出从使能列解码器选择的位线读出的数据。 因此，三维位图数据可以存储在二维中。

    Semiconductor memory device with shift registers for high speed reading and writing
    77.
    发明授权
    Semiconductor memory device with shift registers for high speed reading and writing 失效
    具有移位寄存器的半导体存储器件，用于高速读写

    公开(公告)号：US4745577A

    公开(公告)日：1988-05-17

    申请号：US798284

    申请日：1985-11-15

    申请人： Junji Ogawa ,  Yoshihiro Takemae

    发明人： Junji Ogawa ,  Yoshihiro Takemae

    IPC分类号： H01L27/08 ,  G11C7/10 ,  G11C19/00 ,  G11C7/00

    CPC分类号： G11C7/1075

    摘要： A semiconductor memory device with shift registers used for a video RAM, including a memory cell array, bit lines, and word lines, a pair of shift registers, and transfer gate circuits arranged between the bit lines and the shift registers. Each parallel data transfer circuit is provided between the shift registers for transferring parallel data between the shift registers, so that high-speed reading and writing of data for a CRT display is realized.

    摘要翻译： 具有用于视频RAM的移位寄存器的半导体存储器件，包括存储单元阵列，位线和字线，一对移位寄存器和布置在位线和移位寄存器之间的传输门电路。 每个并行数据传输电路设置在用于在移位寄存器之间传送并行数据的移位寄存器之间，从而实现用于CRT显示器的数据的高速读取和写入。

    Semiconductor integrated circuit device having fuse-type information storing circuit
    78.
    发明授权
    Semiconductor integrated circuit device having fuse-type information storing circuit 失效
    具有熔丝型信息存储电路的半导体集成电路装置

    公开(公告)号：US4707806A

    公开(公告)日：1987-11-17

    申请号：US712149

    申请日：1985-03-15

    申请人： Yoshihiro Takemae ,  Tomio Nakano ,  Takeo Tatematsu ,  Junji Ogawa ,  Takashi Horii ,  Yasuhiro Fujii ,  Masao Nakano ,  Norihisa Tsuge, deceased

    发明人： Yoshihiro Takemae ,  Tomio Nakano ,  Takeo Tatematsu ,  Junji Ogawa ,  Takashi Horii ,  Yasuhiro Fujii ,  Masao Nakano ,  Norihisa Tsuge, deceased

    IPC分类号： H01L27/00 ,  G11C8/10 ,  G11C17/14 ,  G11C17/16 ,  G11C29/00 ,  G11C29/04 ,  H01L23/525 ,  G11C11/00

    CPC分类号： G11C29/785 ,  G11C17/16 ,  G11C8/10 ,  H01L23/5256 ,  H01L2924/0002

    摘要： A device connected between first and second voltage feed lines includes an information storing circuit having a fuse for storing information by blowing or not blowing the fuse, a voltage level conversion circuit connected to at least one of the first and second voltage feed lines and outputting a voltage lower than a voltage between the first and second voltage feed lines to the information storing circuit, and a circuit connected between the first and second voltage feed lines, for outputting a detection signal in response to a voltage value at the fuse in the information storing circuit to which the voltage is applied from the voltage level conversion circuit and which voltage value is varied with the blown or unblown state of the fuse.In a normal operation, the voltage output from the voltage level conversion circuit can be set as low as possible to restrain electromigration caused at the vicinity of the blown portion of the fuse to which the voltage is applied, but higher than the threshold voltage of the information detection circuit.

    摘要翻译： 连接在第一和第二电压馈送线之间的装置包括信息存储电路，该信息存储电路具有熔丝，用于通过吹送或不熔断熔丝来存储信息;电压电平转换电路，连接到第一和第二电压馈送线中的至少一个并输出一个 电压低于第一和第二电压馈送线之间的电压到信息存储电路，以及电路，连接在第一和第二电压馈送线之间，用于响应于信息存储中的熔丝处的电压值输出检测信号 从电压电平转换电路向其施加电压的电路，以及哪个电压值随着保险丝的熔断或非吹出状态而变化。 在正常操作中，可以将从电压电平转换电路输出的电压设置得尽可能低以抑制在施加电压的熔丝的熔断部分附近引起的电迁移，但是高于 信息检测电路。

    Semiconductor memory device
    79.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US4616343A

    公开(公告)日：1986-10-07

    申请号：US788049

    申请日：1985-10-16

    申请人： Junji Ogawa

    发明人： Junji Ogawa

    IPC分类号： G11C7/00 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4094 ,  G11C11/4096 ,  H01L27/10 ,  G11C11/40 ,  G11C13/00

    CPC分类号： G11C11/4096 ,  G11C11/4094

    摘要： A semiconductor memory device including a random access memory cell array, a series/parallel data transfer circuit, transfer gate, an active pull-up circuit, and an active pull-down circuit. The transfer gate is inserted between bit lines of the random access memory cell array and the series/parallel data transfer circuit to carry out parallel transfer of data. Output data of the series/parallel data transfer circuit is simultaneously written in a group of memory cells of selected work lines by turning on the transfer gate and selection of a word line. When data of each output of steps of the series/parallel data transfer circuit is logic "1", the active pull-up circuit charges up a selected bit line of the random access memory cell array. When data of each output of steps of the series/parallel data transfer circuit is logic "0", the active pull-down circuit discharges a selected bit line of the random access memory cell array. One or more of the active pull-up and active pull-down circuits is arranged in the semiconductor memory device.

    摘要翻译： 包括随机存取存储单元阵列，串联/并行数据传输电路，传输门，有源上拉电路和有源下拉电路的半导体存储器件。 传输门被插入到随机存取存储单元阵列的位线和串/并行数据传输电路之间，以执行数据的并行传输。 串行/并行数据传输电路的输出数据通过接通传输门和选择字线而被同时写入选定工作线的一组存储单元。 当串/并行数据传输电路的每个输出的数据为逻辑“1”时，有源上拉电路对随机存取存储单元阵列的所选位线充电。 当串联/并行数据传送电路的每个输出的数据为逻辑“0”时，有源下拉电路对所选择的随机存取存储单元阵列的位线进行放电。 有源上拉和有源下拉电路中的一个或多个布置在半导体存储器件中。

    Nonvolatile semiconductor storage system
    80.
    发明授权
    Nonvolatile semiconductor storage system 有权
    非易失性半导体存储系统

    公开(公告)号：US08949511B2

    公开(公告)日：2015-02-03

    申请号：US13379223

    申请日：2011-09-30

    申请人： Atsushi Ishikawa ,  Koji Sonoda ,  Go Uehara ,  Junji Ogawa ,  Hideyuki Koseki

    发明人： Atsushi Ishikawa ,  Koji Sonoda ,  Go Uehara ,  Junji Ogawa ,  Hideyuki Koseki

    IPC分类号： G06F12/02 ,  G06F13/16 ,  G06F3/06

    CPC分类号： G06F3/0608 ,  G06F3/0626 ,  G06F3/0635 ,  G06F3/0647 ,  G06F3/0658 ,  G06F3/0685 ,  G06F3/0688 ,  G06F12/0246 ,  G06F13/16 ,  G06F13/1684 ,  G06F13/4022

    摘要： A nonvolatile semiconductor storage system has multiple nonvolatile semiconductor storage media, a control circuit having a media interface group (one or more interface devices) coupled to the multiple nonvolatile semiconductor storage media, and multiple switches. The media interface group and the multiple switches are coupled via data buses, and each switch and each of two or more nonvolatile chips are coupled via a data bus. The switch is configured so as to switch a coupling between a data bus coupled to the media interface group and a data bus coupled to any of multiple nonvolatile chips that are coupled to this switch. The control circuit partitions write-target data into multiple data elements, switches a coupling by controlling the multiple switches, and distributively sends the multiple data elements to multiple nonvolatile chips.

    摘要翻译： 非易失性半导体存储系统具有多个非易失性半导体存储介质，具有耦合到多个非易失性半导体存储介质的介质接口组（一个或多个接口器件）和多个开关的控制电路。 介质接口组和多个开关经由数据总线耦合，并且每个开关和两个或更多个非易失性芯片中的每一个经由数据总线耦合。 该开关被配置为切换耦合到媒体接口组的数据总线与耦合到耦合到该开关的多个非易失性芯片中的任何一个的数据总线之间的耦合。 控制电路将写目标数据分成多个数据元，通过控制多个开关切换耦合，并将多个数据元素分配发送到多个非易失性芯片。