公开(公告)号：US06463490B1

公开(公告)日：2002-10-08

申请号：US09447724

申请日：1999-11-24

申请人： Hsuan-Yi Wang ,  Sheng-Chang Peng ,  Nai-Shung Chang

发明人： Hsuan-Yi Wang ,  Sheng-Chang Peng ,  Nai-Shung Chang

IPC分类号： G06F1312

CPC分类号： G06F13/423 ,  G06F13/4031

摘要： The invention provides a method of performing data transfers on a PCI bus between a PCI bus master and a selected device. Wherein, there is a request signal and a grant signal on the PCI bus for a read/write transaction, and during the read/write transaction, the request signal and the grant signal are idle. The method comprises the steps of: (a) driving a first ready signal by the PCI bus master; (b) driving a second read signal by the selected device in response to the first ready signal, which initiates the read/write transaction; (c) using the request signal and the grant signal as a data transfer strobe signal during the write and read transaction, respectively, the data transfer strobe signal has a plurality of clocks; and (d) performing the data transfers on rising and falling edges of the clocks of the data transfer strobe signal.

摘要翻译： 本发明提供了一种在PCI总线主机和所选设备之间的PCI总线上执行数据传输的方法。 其中，在PCI总线上存在用于读/写事务的请求信号和授权信号，并且在读/写事务期间，请求信号和授权信号是空闲的。 该方法包括以下步骤：（a）由PCI总线主机驱动第一就绪信号; （b）响应于启动所述读/写交易的所述第一就绪信号，由所选择的设备驱动第二读信号; （c）分别在写入和读取事务期间使用请求信号和授权信号作为数据传输选通信号，数据传输选通信号具有多个时钟; 和（d）在数据传输选通信号的时钟的上升沿和下降沿执行数据传输。

公开(公告)号：US06362996B1

公开(公告)日：2002-03-26

申请号：US09761944

申请日：2001-01-17

申请人： Nai-Shung Chang

发明人： Nai-Shung Chang

IPC分类号： G11C502

摘要： A terminating circuit module and a computer system using the same, in which a voltage regulator and a plurality of pull-up resistors can be provided on the terminating circuit module by the mainboard producer to reduce the area of the printed circuit board of the mainboard. Also, a nonvolatile memory can be provided on the terminating circuit module to store the information representing such terminating circuit module. The computer can automatically read the configuration of the memory and the terminating circuit module such as the slotted positions for the terminating circuit module and the memory module to prevent users from using the terminating circuit module in an incorrect way.

公开(公告)号：US06286097B1

公开(公告)日：2001-09-04

申请号：US09267881

申请日：1999-03-11

申请人： Nai-Shung Chang ,  Yung-Hui Chen ,  Hui-Li Chou

发明人： Nai-Shung Chang ,  Yung-Hui Chen ,  Hui-Li Chou

IPC分类号： G06F9445

CPC分类号： G06F13/4226

摘要： A computer chipset having reduced peripheral pins for accessing a conventional ROM in a computer system is disclosed. There is a switching circuit within the chipset. When the computer is turned on, a booting control circuit activates a booting enabling signal, so that booting programs can be accessed from the ROM through the switching circuit and are executed in a main processor. Subsequently, contents stored in the ROM are moved to a main memory and the booting enabling signal is inactivated by the booting control circuit to allow a peripheral control circuit to communicate with peripheral devices. In this way, chipset having a low pin count (LPC) interface circuit can share the peripheral pins of the chipset to access the conventional ROMs, so that the production costs can be reduced.

摘要翻译： 公开了一种具有减少用于访问计算机系统中的常规ROM的外围引脚的计算机芯片组。 芯片组内有开关电路。 当计算机打开时，启动控制电路激活启动使能信号，从而可以通过切换电路从ROM访问引导程序，并在主处理器中执行。 随后，存储在ROM中的内容被移动到主存储器，并且引导启动信号被引导控制电路去激活，以允许外围控制电路与外围设备通信。 以这种方式，具有低引脚数（LPC）接口电路的芯片组可以共享芯片组的外围引脚以访问常规的ROM，从而可以降低生产成本。

公开(公告)号：US06266786B1

公开(公告)日：2001-07-24

申请号：US09199845

申请日：1998-11-25

申请人： Nai-Shung Chang

发明人： Nai-Shung Chang

IPC分类号： G06F126

CPC分类号： G06F1/305

摘要： A method and circuit is provided for safeguarding the data stored in a CMOS RAM (Complementary Metal-Oxide Semiconductor Random Access Memory) unit in a computer system, such as an IBM-compatible personal computer (PC), when the battery unit used to power the CMOS RAM unit is below working level. By this method and circuit, when the PC is powered off, the current power level of the battery unit is detected to see whether it is below working level; if yes, the main power of the PC is turned on; then the data currently stored in the CMOS RAM unit are moved to a backup-data storage unit such as the hard disk; and after this, the main power is turned off again. At the next time the PC is powered on, the data currently stored in the backup-data storage unit are moved back to the CMOS RAM unit; and after this, a message is displaying on the monitor screen requesting the user to replace the CMOS RAM battery with a new one.

摘要翻译： 提供了一种方法和电路，用于在电池单元用于供电时保护存储在计算机系统中的诸如IBM兼容个人计算机（PC）的计算机系统中的CMOS RAM（互补金属氧化物半导体随机存取存储器）单元中的数据 CMOS RAM单元低于工作电平。 通过这种方法和电路，当PC断电时，检测电池单元的当前功率电平，看其是否低于工作电平; 如果是，PC的主电源打开; 则将当前存储在CMOS RAM单元中的数据移动到诸如硬盘的备份数据存储单元; 此后，主电源再次关闭。 在下一次PC打开电源时，当前存储在备份数据存储单元中的数据被移回到CMOS RAM单元; 此后，在监视器屏幕上显示一条消息，请求用户用新的CMOS RAM电池替换CMOS RAM电池。

公开(公告)号：US07689847B2

公开(公告)日：2010-03-30

申请号：US11423718

申请日：2006-06-13

申请人： Nai-Shung Chang ,  Chia-Hsing Yu

发明人： Nai-Shung Chang ,  Chia-Hsing Yu

IPC分类号： G06F1/00

CPC分类号： G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/124 ,  Y02D10/126 ,  Y02D10/172

摘要： A method for dynamically increasing the data processing capability of a computer system is provided. The computer system comprises a processor, a memory and a chipset. The data processing capability of the computer system is classified into a predetermined number of performance enhancing modes. At least one performance enhancing mode transition condition is checked to determine whether to automatically raise the performance enhancing mode of the computer system. The processor is suspended from using the processor bus during the transition of the performance enhancing mode of the computer system. The performance enhancing mode of the computer system is raised by increasing a first working frequency of the processor, a second working frequency of the processor bus and a third working frequency of the memory. The data processing rate of the computer system is further increased when the performance enhancing mode of the computer system is further raised.

摘要翻译： 提供了一种用于动态提高计算机系统的数据处理能力的方法。 计算机系统包括处理器，存储器和芯片组。 计算机系统的数据处理能力被分为预定数量的性能增强模式。 检查至少一个性能增强模式转换条件以确定是否自动提高计算机系统的性能增强模式。 处理器在计算机系统的性能提升模式转换期间被暂停使用处理器总线。 通过增加处理器的第一工作频率，处理器总线的第二工作频率和存储器的第三工作频率来提高计算机系统的性能增强模式。 当计算机系统的性能提升模式进一步提高时，计算机系统的数据处理速度进一步提高。

公开(公告)号：US07298028B2

公开(公告)日：2007-11-20

申请号：US11257593

申请日：2005-10-24

申请人： Chih-Hsiung Lin ,  Nai-Shung Chang

发明人： Chih-Hsiung Lin ,  Nai-Shung Chang

IPC分类号： H01L23/495

CPC分类号： H05K1/0209 ,  H01L23/367 ,  H01L23/3735 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/10734

摘要： A printed circuit board (PCB) for a package substrate of a multi-package module (MPM). The PCB comprises a substrate and a heat sink thereon. The heat sink comprises a first portion under the package substrate of the MPM. The heat sink further comprises a second portion adjacent to the first portion, comprising at least one fin.

摘要翻译： 一种用于多封装模块（MPM）的封装基板的印刷电路板（PCB）。 PCB包括衬底和其上的散热器。 散热器包括在MPM的封装衬底下方的第一部分。 散热器还包括邻近第一部分的第二部分，包括至少一个散热片。

公开(公告)号：US20060203740A1

公开(公告)日：2006-09-14

申请号：US11162608

申请日：2005-09-16

申请人： Nai-Shung Chang ,  Chia-Hsing Yu

发明人： Nai-Shung Chang ,  Chia-Hsing Yu

IPC分类号： H04L1/00

CPC分类号： G06F11/0745 ,  G06F11/0757 ,  G06F11/3471 ,  G06F11/349 ,  G06F2201/81 ,  G06F2201/88

摘要： Method and related apparatus for monitoring access modules, like memory or input/output modules, linked with a system bus of a computer system. In the present invention, access modules to be monitored and their corresponding monitoring intervals are preset. When a given access module initiates information exchange via the system bus, it is checked to see if the given access module matches any of the access modules to be monitored. If a match is found, a countdown is started from the corresponding monitoring interval. If the given access module completes the information exchange before the countdown finishes, the given access module is determined to be normal. Otherwise, a predetermined timeout event is executed for responding to a potential problem of the given access module.

摘要翻译： 用于监视与计算机系统的系统总线链接的访问模块（如存储器或输入/输出模块）的方法和相关装置。 在本发明中，预先设定要监视的访问模块及其对应的监视间隔。 当给定的访问模块通过系统总线发起信息交换时，检查给定的访问模块是否匹配要监视的任何访问模块。 如果找到匹配，则从相应的监视间隔开始倒计时。 如果给定的访问模块在倒计时完成之前完成信息交换，则给定的访问模块被确定为正常。 否则，执行预定的超时事件以响应给定访问模块的潜在问题。

公开(公告)号：US07007175B2

公开(公告)日：2006-02-28

申请号：US10005627

申请日：2001-12-04

申请人： Nai-Shung Chang ,  Chia-Hsing Yu ,  Chia-Hsin Chen

发明人： Nai-Shung Chang ,  Chia-Hsing Yu ,  Chia-Hsin Chen

IPC分类号： G06F1/26

CPC分类号： G06F1/3275 ,  G06F1/3203 ,  Y02D10/14 ,  Y02D50/20

摘要： A motherboard with reduced power consumption is disclosed. The motherboard has a memory module slot, a DDR termination array, and a control chip. The DDR termination array couples to the memory module slot and provides a termination resistor that has one terminal coupled to a voltage source. The control chip provides a control signal. When the motherboard enters a power saving mode or before the memory module being inserted in the memory module slot, the control signal gives an indication to the DDR termination array for cutting off the connection between the termination resistor and the memory module slot. A switch and several termination resistors may substitute the DDR termination array as requirements. The control chip provides the control signal to open the switch and therefore cuts off the connections between termination resistors and the voltage source to achieve the power-conserving purpose.

公开(公告)号：US06745275B2

公开(公告)日：2004-06-01

申请号：US09756073

申请日：2001-01-08

申请人： Nai-Shung Chang

发明人： Nai-Shung Chang

IPC分类号： G06F1314

CPC分类号： G11C5/06 ,  G06F1/26 ,  G11C5/04 ,  G11C8/06 ,  G11C8/12 ,  H05K1/0246 ,  H05K1/0262 ,  H05K1/14 ,  H05K1/141 ,  H05K2201/044 ,  H05K2201/10022 ,  H05K2201/10159

摘要： A feedback system capable of accommodating different memory module loading. The feedback system utilizes the signal received by the data strobe feedback pin of a control chipset to simulate or to obtain memory module loading information so that timing of the data signal and data strobe signal can be adjusted accordingly. Therefore, data can be accurately written to or read from the memory module. The embodiment of this invention includes using a variable reference voltage source and a comparator to adjust the timing of the signal to the data strobe feedback pin, using independent simulating loads circuit and specially designed memory module with simulating load, and using a data strobe signal circuit that includes complete memory module loading.

摘要翻译： 一种能够适应不同存储器模块负载的反馈系统。 反馈系统利用由控制芯片组的数据选通反馈引脚接收的信号来模拟或获得存储器模块负载信息，从而可以相应地调整数据信号和数据选通信号的定时。 因此，可以将数据准确地写入或从存储器模块读取。 本发明的实施例包括使用可变参考电压源和比较器，使用独立的模拟负载电路和专门设计的具有模拟负载的存储器模块来调整信号到数据选通反馈引脚的定时，并使用数据选通信号电路 包括完整的内存模块加载。

公开(公告)号：US06681286B2

公开(公告)日：2004-01-20

申请号：US09756324

申请日：2001-01-08

申请人： Nai-Shung Chang ,  Chia-Hsing Yu

发明人： Nai-Shung Chang ,  Chia-Hsing Yu

IPC分类号： G06F1300

CPC分类号： G11C5/06 ,  G06F1/26 ,  G11C5/04 ,  G11C8/06 ,  G11C8/12 ,  H05K1/0246 ,  H05K1/0262 ,  H05K1/14 ,  H05K1/141 ,  H05K2201/044 ,  H05K2201/10022 ,  H05K2201/10159

摘要： A control chipset having dual-definition data pins capable of reducing circuit layout to memory module slots. Using dual-definition data pins of the control chipset and multiplexing/de-multiplexing devices, the control chipset is able to sense the particular type of memory modules plugged into memory slots automatically and hence assigning the function to each data pin accordingly. Consequently, circuit layout from the control chipset to the data pins of far off memory slots is simplified and overall circuit length is greatly reduced.

摘要翻译： 具有能够将电路布局降低到存储器模块时隙的双精度数据引脚的控制芯片组。 使用控制芯片组和复用/解复用器件的双重定义数据引脚，控制芯片组能够自动检测插入存储器插槽的特定类型的存储器模块，从而相应地将功能分配给每个数据引脚。 因此，简化了从控制芯片组到远离存储器插槽的数据引脚的电路布局，并大大减少了整体电路长度。