公开(公告)号：US11935857B2

公开(公告)日：2024-03-19

申请号：US17952080

申请日：2022-09-23

Applicant: Intel Corporation

Inventor： Kristof Darmawaikarta ,  Robert May ,  Sashi Kandanur ,  Sri Ranga Sai Boyapati ,  Srinivas Pietambaram ,  Steve Cho ,  Jung Kyu Han ,  Thomas Heaton ,  Ali Lehaf ,  Ravindranadh Eluri ,  Hiroki Tanaka ,  Aleksandar Aleksov ,  Dilan Seneviratne

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L24/17 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L24/09 ,  H01L24/11 ,  H01L2924/01029 ,  H01L2924/0105

Abstract: Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).

公开(公告)号：US11894324B2

公开(公告)日：2024-02-06

申请号：US17528049

申请日：2021-11-16

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Telesphor Kamgaing ,  Sri Ranga Sai Boyapati ,  Kristof Darmawikarta ,  Eyal Fayneh ,  Ofir Degani ,  David Levy ,  Johanna M. Swan

IPC: H01L23/66 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/66 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L24/17 ,  H01L2223/6627 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/19033

Abstract: In-package radio frequency (RF) waveguides as high bandwidth chip-to-chip interconnects and methods for using the same are disclosed. In one example, an electronic package includes a package substrate, first and second silicon dies or tiles, and an RF waveguide. The first and second silicon dies or tiles are attached to the package substrate. The RF waveguide is formed in the package substrate and interconnects the first silicon die or tile with the second silicon die or tile.

公开(公告)号：US11876053B2

公开(公告)日：2024-01-16

申请号：US17144130

申请日：2021-01-07

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Chia-Pin Chiu ,  Aleksandar Aleksov ,  Hinmeng Au ,  Stefanie M. Lotz ,  Johanna M. Swan ,  Sujit Sharan

IPC: H01L23/538 ,  H01L23/13 ,  H01L23/00 ,  H01L25/065 ,  H01L21/683

CPC classification number: H01L23/5385 ,  H01L23/13 ,  H01L23/5381 ,  H01L24/14 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L21/6835 ,  H01L24/17 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/141 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/19107 ,  H01L2924/351 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/49175 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/45147 ,  H01L2924/00 ,  H01L2924/01015 ,  H01L2924/00 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/0401 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/00011 ,  H01L2224/0401

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

公开(公告)号：US11854834B2

公开(公告)日：2023-12-26

申请号：US17677105

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Kristof Kuwawi Darmawikarta ,  Robert May ,  Sri Ranga Sai Boyapati ,  Srinivas V. Pietambaram ,  Chung Kwang Christopher Tan ,  Aleksandar Aleksov

IPC: H01L21/48 ,  H01L23/498

CPC classification number: H01L21/4857 ,  H01L21/481 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49838

Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.

公开(公告)号：US11694962B2

公开(公告)日：2023-07-04

申请号：US17229991

申请日：2021-04-14

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Aleksandar Aleksov ,  Feras Eid ,  Telesphor Kamgaing ,  Johanna M. Swan

IPC: H01L23/538 ,  B81B7/00 ,  H01L23/28 ,  H01L23/552 ,  H01L21/56

CPC classification number: H01L23/5385 ,  B81B7/0006 ,  B81B7/007 ,  H01L21/565 ,  H01L23/28 ,  H01L23/5384 ,  H01L23/552

Abstract: Embodiments may relate to a microelectronic package that includes an overmold material, a redistribution layer (RDL) in the overmold material, and a die in the overmold material electrically coupled with the RDL on an active side of the die. The RDL is configured to provide electrical interconnection within the overmold material and includes at least one mold interconnect. The microelectronic package may also include a through-mold via (TMV) disposed in the overmold material and electrically coupled to the RDL by the mold interconnect. In some embodiments, the microelectronics package further includes a surface mount device (SMD) in the overmold material. The microelectronics package may also include a substrate having a face on which the overmold is disposed.

公开(公告)号：US20230197620A1

公开(公告)日：2023-06-22

申请号：US17558304

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Veronica Strong ,  Aleksandar Aleksov ,  Georgios Dogiamis ,  Telesphor Kamgaing ,  Neelam Prabhu Gaunkar ,  Brandon Rawlings

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/065

CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L25/0652 ,  H01L25/0657 ,  H01L23/49866

Abstract: Methods, systems, apparatus, and articles of manufacture are disclosed for integrated circuit package substrates with high aspect ratio through glass vias. An example microelectronic package including a glass substrate including a via, the via including a high aspect ratio. The example microelectronic package further including a seed layer extending substantially evenly along an inner wall of the via.

公开(公告)号：US11641711B2

公开(公告)日：2023-05-02

申请号：US17695118

申请日：2022-03-15

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Aleksandar Aleksov ,  Feras Eid ,  Telesphor Kamgaing ,  Johanna M. Swan

IPC: H05K1/16 ,  H05K1/02 ,  H05K3/12 ,  H05K3/40 ,  H05K9/00

Abstract: Embodiments may relate to a microelectronic package or a die thereof which includes a die, logic, or subsystem coupled with a face of the substrate. An inductor may be positioned in the substrate. Electromagnetic interference (EMI) shield elements may be positioned within the substrate and surrounding the inductor. Other embodiments may be described or claimed.

公开(公告)号：US11621192B2

公开(公告)日：2023-04-04

申请号：US17338296

申请日：2021-06-03

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Feras Eid ,  Telesphor Kamgaing ,  Georgios Dogiamis ,  Johanna M. Swan

IPC: H01L21/768 ,  H01L23/00

Abstract: Disclosed herein are methods to fabricate inorganic dies with organic interconnect layers and related structures and devices. In some embodiments, an integrated circuit (IC) structure may be formed to include an inorganic die and one or more organic interconnect layers on the inorganic die, wherein the organic interconnect layers include an organic dielectric. An example method includes forming organic interconnect layers over an inorganic interconnect substrate and forming passive components in the organic interconnect layer. The organic interconnect layers comprise a plurality of conductive metal layers through an organic dielectric material. The plurality of conductive metal layers comprises electrical pathways. the passive components are electrically coupled to the electrical pathways.

公开(公告)号：US20230098957A1

公开(公告)日：2023-03-30

申请号：US17485235

申请日：2021-09-24

Applicant: INTEL CORPORATION

Inventor： Feras Eid ,  Aleksandar Aleksov ,  Adel Elsherbini ,  Henning Braunisch

IPC: H01L23/00

Abstract: A conformal power delivery structure, a three-dimensional (3D) stacked die assembly, a system including the 3D stacked die assembly, and a method of forming the conformal power delivery structure. The power delivery structure includes a package substrate, a die adjacent to and electrically coupled to the package substrate; a first power plane adjacent the upper surface of the package substrate and electrically coupled thereto; a second power plane at least partially within recesses defined by the first power plane and having a lower surface that conforms with the upper surface of the first power plane; and a dielectric material between the first power plane and the second power plane.

公开(公告)号：US20230094979A1

公开(公告)日：2023-03-30

申请号：US17484299

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Henning Braunisch ,  Feras Eid ,  Adel Elsherbini ,  Stephen Morein ,  Yoshihiro Tomita ,  Thomas L. Sounart ,  Johanna Swan ,  Brandon M. Rawlings

IPC: H01L23/50 ,  H01L23/532

Abstract: Technologies for conformal power delivery structures near high-speed signal traces are disclosed. In one embodiment, a dielectric layer may be used to keep a power delivery structure spaced apart from high-speed signal traces, preventing deterioration of signals on the high-speed signal traces due to capacitive coupling to the power delivery structure.