公开(公告)号：US20240203926A1

公开(公告)日：2024-06-20

申请号：US18593775

申请日：2024-03-01

Applicant: Intel Corporation

Inventor： Feras Eid ,  Joe Walczyk ,  Weihua Tang ,  Akhilesh Rallabandi ,  Marco Aurelio Cartas Ayala

IPC: H01L23/00

CPC classification number: H01L24/29 ,  H01L2224/29287 ,  H01L2224/29293 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2924/14 ,  H01L2924/351

Abstract: An integrated circuit (IC) die structure comprises a substrate material comprising silicon. Integrated circuitry is over a first side of the substrate material. A composite layer is in direct contact with a second side of the substrate material. The second side is opposite the first side. The composite layer comprises a first constituent material associated with a first linear coefficient of thermal expansion (CTE), and a first thermal conductivity exceeding that of the substrate. The composite layer also comprises a second constituent material associated with a second CTE that is lower than the first, and a second thermal conductivity exceeding that of the substrate.

公开(公告)号：US20240063091A1

公开(公告)日：2024-02-22

申请号：US17891735

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Scot Kellar ,  Yoshihiro Tomita ,  Rajiv Mongia ,  Kimin Jun ,  Shawna Liff ,  Wenhao Li ,  Johanna Swan ,  Bhaskar Jyoti Krishnatreya ,  Debendra Mallik ,  Krishna Vasanth Valavala ,  Lei Jiang ,  Xavier Brun ,  Mohammad Enamul Kabir ,  Haris Khan Niazi ,  Jiraporn Seangatith ,  Thomas Sounart

IPC: H01L23/473 ,  H01L23/00 ,  H01L25/065 ,  H01L23/367 ,  H01L23/373

CPC classification number: H01L23/473 ,  H01L24/08 ,  H01L25/0652 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/3677 ,  H01L23/3675 ,  H01L23/3732 ,  H01L23/3738 ,  H01L2924/3511 ,  H01L2224/08145 ,  H01L2224/08121 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/182 ,  H01L2924/186

Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more chiplets bonded to a base die and an inorganic dielectric material adjacent the chiplets and over the base die. The multichip composite device is coupled to a structural member that is made of or includes a heat conducting material, or has integrated fluidic cooling channels to conduct heat from the chiplets and the base die.

公开(公告)号：US20240030098A1

公开(公告)日：2024-01-25

申请号：US18366734

申请日：2023-08-08

Applicant: Intel Corporation

Inventor： Feras Eid ,  Telesphor Kamgaing ,  Georgios Dogiamis ,  Aleksandar Aleksov ,  Johanna M. Swan

IPC: H01L23/427 ,  H01L23/38 ,  H01L23/373 ,  H01L23/31 ,  H01L23/48 ,  H03H9/46 ,  H01L23/66

CPC classification number: H01L23/427 ,  H01L23/38 ,  H01L23/373 ,  H01L23/3157 ,  H01L23/481 ,  H03H9/46 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6644 ,  H01L2223/6677

Abstract: Disclosed herein are structures and assemblies that may be used for thermal management in integrated circuit (IC) packages.

公开(公告)号：US20230317556A1

公开(公告)日：2023-10-05

申请号：US17710658

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Akhilesh Rallabandi ,  Feras Eid

IPC: H01L23/467

CPC classification number: H01L23/467

Abstract: A modification structure may be formed within a chassis of an electronic product to improve its thermal dissipation systems, to lessen its weight, and/or to enhance its durability, while maintaining the industrial design/esthetics/ergonomics thereof, wherein the modification structure may comprise a plurality of fused modification material particles. The modification structures may have a higher thermal conductivity than the chassis, may have a lower thermal conductivity than the chassis, may have a lower density than the chassis, and/or may have a higher yield strength than the chassis. In a specific example, the modification structure may extend entirely through the chassis and be sufficiently porous to allow air flow to assist in heat dissipation from the electronic product.

公开(公告)号：US20230317546A1

公开(公告)日：2023-10-05

申请号：US17710670

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Xavier Brun ,  Nabankur Deb ,  Feras Eid

IPC: H01L23/367 ,  H01L21/78

CPC classification number: H01L23/367 ,  H01L21/78 ,  H01L23/3135

Abstract: Embodiments are directed to a device having an overhang portion. In some embodiments, a main body structure of the device comprises an IC die and an exterior surface of the main body structure comprises the overhang portion. The overhang portion adjoins a sidewall structure of the main body structure of the device, which is substantially perpendicular to a backside of the IC die. In some embodiments, the main body structure further comprises a package mold structure, which comprises the overhang portion.

公开(公告)号：US20230282542A1

公开(公告)日：2023-09-07

申请号：US17685060

申请日：2022-03-02

Applicant: Intel Corporation

Inventor： Wenhao Li ,  Feras Eid ,  Yoshihiro Tomita

IPC: H01L23/373

CPC classification number: H01L23/3733 ,  H01L23/3732

Abstract: An integrated circuit assembly may be fabricated to include an integrated circuit device having a backside surface and a metal matrix composite layer on the backside surface, wherein the metal matrix composite layer has a filler material disposed therein to reduce the coefficient of thermal expansion thereof. The filler material may be a plurality of graphitic carbon filler particles, wherein the plurality of graphitic carbon filler particles has an average aspect ratio of greater than about 10, or the filler material may be a plurality of diamond particles, wherein the filler material is clad with a metal material.

公开(公告)号：US20230271445A1

公开(公告)日：2023-08-31

申请号：US17680839

申请日：2022-02-25

Applicant: Intel Corporation

Inventor： Feras Eid ,  Wenhao Li ,  Jiraporn Seangatith ,  Paul Diglio ,  Xavier Brun

IPC: B41N1/24

CPC classification number: B41N1/248

Abstract: Reusable composite stencils for spray processes, particularly for spray processes used in the fabrication of integrated circuit devices, may be fabricated having a permanent core and at least one sacrificial material layer. Thus, in operation, when a predetermined amount of the sacrificial material layer has been ablated away by a material being sprayed in the spray process, the remaining sacrificial material layer may be removed and reapplied to its original thickness. Therefore, the permanent core, which is usually expensive and/or difficult to fabricate, may be repeatedly reused.

公开(公告)号：US20230266070A1

公开(公告)日：2023-08-24

申请号：US17677829

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Feras Eid ,  Akhilesh Rallabandi

IPC: F28D15/04 ,  F28D15/02 ,  H05K7/20

CPC classification number: F28D15/046 ,  F28D15/043 ,  F28D15/0275 ,  H05K7/20336

Abstract: A heat dissipation device for an integrated circuit assembly may be fabricated to include at least one heat pipe that is at least partially embedded in a base plate that is formed with an additive manufacturing process, such as cold spraying. Embedding the at least one heat pipe in the base plate, rather than soldering the heat pipe to the base plate, eliminates the thermal bottleneck presented by the soldering material and reduces the overall height or thickness of the integrated circuit assembly.

公开(公告)号：US11688660B2

公开(公告)日：2023-06-27

申请号：US16534820

申请日：2019-08-07

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Feras Eid ,  Georgios Dogiamis ,  Telesphor Kamgaing ,  Johanna M. Swan

IPC: H01Q23/00 ,  H01Q1/52 ,  H01Q1/02 ,  H01L23/36 ,  H01L23/538 ,  H01L23/552

CPC classification number: H01L23/36 ,  H01L23/5381 ,  H01L23/552

Abstract: Embodiments may relate to a radio frequency (RF) multi-chip module that includes a first RF die and a second RF die. The first and second RF dies may be coupled with a package substrate at an inactive side of the respective dies. A bridge may be coupled with an active side of the first and second RF dies die such that the first and second RF dies are communicatively coupled through the bridge, and such that the first and second RF dies are at least partially between the package substrate and the bridge. Other embodiments may be described or claimed.

公开(公告)号：US11621236B2

公开(公告)日：2023-04-04

申请号：US16728278

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Feras Eid ,  Veronica Aleman Strong ,  Aleksandar Aleksov ,  Adel A. Elsherbini ,  Johanna M. Swan

IPC: H01L23/60 ,  H01L23/34 ,  H01L23/498 ,  H01L23/532 ,  H01L23/13 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10

Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). In some embodiments, an IC package support may include: a first conductive structure; a second conductive structure; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a positive temperature coefficient material.