公开(公告)号：US11646373B2

公开(公告)日：2023-05-09

申请号：US17516994

申请日：2021-11-02

Applicant: International Business Machines Corporation

Inventor： Christopher J. Waskiewicz ,  Ruilong Xie ,  Jay William Strane ,  Hemanth Jagannathan

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/7827 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a substrate, at least one semiconductor vertical fin extending from the substrate, a bottom source/drain region disposed beneath the at least one semiconductor vertical fin, and first and second isolation regions on respective longitudinal sides of the semiconductor vertical fin. Each of the first and second isolation regions extend vertically above the bottom source/drain region. A bottom spacer is disposed on the first and second isolation regions. A spacer segment of the bottom spacer is disposed on a first upper surface portion of the bottom source/drain region adjacent the first isolation region. A dielectric liner underlies at least portions of the first and second isolation regions. A dielectric segment of the dielectric liner is disposed on a second upper surface portion of the bottom source/drain region adjacent the second isolation region. At least one functional gate structure is disposed on the semiconductor vertical fin.

公开(公告)号：US20230093343A1

公开(公告)日：2023-03-23

申请号：US17482940

申请日：2021-09-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Andrew Gaul ,  Julien Frougier ,  Ruilong Xie ,  Andrew M. Greene ,  Christopher J. Waskiewicz

IPC: H01L29/76 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: A stacked device is provided. The stacked device includes a plurality of dielectric support bridges on a substrate, and a first two-dimensional (2D) channel layer on each of the plurality of dielectric support bridges. The stacked device further includes a gate dielectric sheet on the first two-dimensional (2D) channel layer, and a second two-dimensional (2D) channel layer on the first two-dimensional (2D) channel layer. The stacked device further includes a second gate dielectric layer on the gate dielectric sheets.

公开(公告)号：US11351811B2

公开(公告)日：2022-06-07

申请号：US16888126

申请日：2020-05-29

Applicant: International Business Machines Corporation

Inventor： Michael Rizzolo ,  Marc A. Bergendahl ,  Christopher J. Waskiewicz ,  Christopher J. Penny

IPC: G06K19/06 ,  B42D25/369 ,  G06K19/18 ,  G06K19/12 ,  B42D25/373 ,  G06F21/44 ,  B42D25/333 ,  G06F21/12

Abstract: An article is authenticated by providing a magnetic security mark in the form of an optically-passive randomly-generated nanoscale magnetic pattern. The pattern is pre-imaged and this reference image is uploaded to a secure database along with an identifier for the article such as a serial number. A user of the article verifies its authenticity by scanning it magnetically to obtain a scanned image of the magnetic pattern. The serial number is used to retrieve the previously uploaded reference image which is compared to the scanned image. If the images match, the article's authenticity is confirmed. A single article may have multiple magnetic security marks, each unique, placed at predetermined, non-uniform locations. The magnetic patterns are generated using thin film deposition of yttrium iron garnet. In one embodiment the article is a physical key having additional security features, such as mechanical features and a radio-frequency identification chip.

公开(公告)号：US11263059B2

公开(公告)日：2022-03-01

申请号：US16125466

申请日：2018-09-07

Applicant: International Business Machines Corporation

Inventor： Jonathan Fry ,  Christopher J. Penny ,  Marc Bergendahl ,  Christopher J. Waskiewicz ,  Jean Wynne ,  James Demarest

IPC: G06F9/46 ,  G06F9/50 ,  G06F9/48 ,  H04L9/06

Abstract: An example operation may include one or more of connecting, by a load leveler, to a blockchain network comprising a plurality of nodes and configured to store a common work item, computing, by the load leveler, loads across the plurality of the nodes that need to execute the common work item upon completion of current tasks, determining, by the load leveler, a network load impact based on execution of a common blockchain consensus checking process on the network nodes, executing, by the load leveler, a work assessment process based on the loads computed across the plurality of the nodes and on the determined network load impact of the blockchain network, and assigning, by the load leveler, new tasks to the nodes based on results of the execution of the work assessment process.

公开(公告)号：US20210408261A1

公开(公告)日：2021-12-30

申请号：US16910296

申请日：2020-06-24

Applicant: International Business Machines Corporation

Inventor： Chen Zhang ,  Christopher J. Waskiewicz ,  Shahab Siddiqui ,  Ruilong Xie

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78

Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a top spacer trench adjacent to an upper region of the channel fin. An oxygen-blocking layer is deposited within the top spacer trench and over the upper region of the channel fin. A top spacer is formed within the top spacer trench and over a portion of the oxygen-blocking layer that is within the top spacer trench. The oxygen-blocking layer includes an oxygen gettering material.

公开(公告)号：US20210287988A1

公开(公告)日：2021-09-16

申请号：US16814305

申请日：2020-03-10

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Christopher J. Waskiewicz ,  Kangguo Cheng ,  Chih-Chao Yang

IPC: H01L23/535 ,  H01L21/768

Abstract: Interconnect structures and methods for forming the interconnect structures generally include forming a bulk metal encapsulated in first and second interlayer dielectrics, a liner layer about a lower surface of the bulk metal and a metal cap layer about an upper surface of the bulk metal. The liner layer is in the first interlayer dielectric and the metal cap layer is in the second interlayer dielectric, wherein liner layer and the metal cap layer are different metals.

公开(公告)号：US10943992B2

公开(公告)日：2021-03-09

申请号：US16407564

申请日：2019-05-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Christopher J. Waskiewicz ,  Michael P. Belyansky ,  Brent Alan Anderson ,  Muthumanickam Sankarapandian ,  Puneet Suvarna ,  Hiroaki Niimi

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L21/02 ,  H01L29/417 ,  H01L21/311

Abstract: An integrated semiconductor device having a substrate and a vertical field-effect transistor (FET) disposed on the substrate. The vertical FET includes a fin and a bottom spacer. The bottom spacer further includes a first spacer layer and a second spacer layer formed on top of the first spacer layer. The bottom spacer provides for a symmetrical straight alignment at a bottom junction between the bottom spacer and the fin.

公开(公告)号：US20210005735A1

公开(公告)日：2021-01-07

申请号：US17026451

申请日：2020-09-21

Applicant: International Business Machines Corporation

Inventor： Christopher J. Waskiewicz ,  Su Chen Fan ,  Hari Prasad Amanapu ,  Hemanth Jagannathan

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/768 ,  H01L29/78

Abstract: A semiconductor includes a semiconductor substrate having a bottom source/drain region and a vertical semiconductor fin having a bottom end that contacts the semiconductor substrate. The semiconductor device further includes a top source/drain region on a top end of the vertical semiconductor. The top source/drain region is separated from the semiconductor substrate by the vertical semiconductor fin. The semiconductor device further includes an electrically conductive cap on an outer surface of the top source/drain region.

公开(公告)号：US10770653B1

公开(公告)日：2020-09-08

申请号：US16515461

申请日：2019-07-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Christopher J. Penny ,  Marc A. Bergendahl ,  Michael Rizzolo ,  Christopher J. Waskiewicz

IPC: H01L43/12 ,  G11C11/16 ,  H01L27/22

Abstract: A method is presented for reducing dielectric gouging during etching processes of a magnetoresistive random access memory (MRAM) structure including an MRAM region and a non-MRAM region. The method includes forming protective layers in the MRAM region to preserve integrity of underlying dielectric layers, forming a bottom electrode in direct contact with the protective layers, and constructing an MRAM pillar over the bottom electrode, wherein the MRAM pillar includes a magnetic tunnel junction (MTJ) stack and a top electrode.

公开(公告)号：US20200075737A1

公开(公告)日：2020-03-05

申请号：US16571256

申请日：2019-09-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Choonghyun Lee ,  Christopher J. Waskiewicz ,  Alexander Reznicek ,  Hemanth Jagannathan

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/08 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/45 ,  H01L29/78

Abstract: A method is presented for forming a wrap-around-contact. The method includes forming a bottom source/drain region adjacent a plurality of fins, disposing encapsulation layers over the plurality of fins, recessing at least one of the encapsulation layers to expose top portions of the plurality of fins, and for forming top spacers adjacent the top portions of the plurality of fins. The method further includes disposing a sacrificial liner adjacent the encapsulation layers, recessing the top spacers, forming top source/drain regions over the top portions of the plurality of fins, removing the sacrificial liner to create trenches adjacent the top source/drain regions, and depositing a metal liner within the trenches and over the top source/drain regions such that the wrap-around-contact is defined to cover an upper area of the top source/drain regions.