公开(公告)号：US10560081B2

公开(公告)日：2020-02-11

申请号：US15632836

申请日：2017-06-26

Applicant: Intel Corporation

Inventor： Mahesh Wagh ,  Zuoguo J. Wu ,  Venkatraman Iyer ,  Gerald S. Pasdast ,  Todd A. Hinck ,  David M. Lee ,  Narasimha R. Lanka

IPC: H03K5/26 ,  G01R31/04 ,  H03L9/00 ,  G06F1/3296 ,  G06F13/42 ,  H03K5/131

Abstract: In an example, a system and method for centering in a high-performance interconnect (HPI) are disclosed. When an interconnect is powered up from a dormant state, it may be necessary to “center” the clock signal to ensure that data are read at the correct time. A multi-phase method may be used, in which a first phase comprises a reference voltage sweep to identify an optimal reference voltage. A second phase comprises a phase sweep to identify an optimal phase. A third sweep comprises a two-dimensional “eye” phase, in which a plurality of values within a two-dimensional eye derived from the first two sweeps are tested. In each case, the optimal value is the value that results in the fewest bit error across multiple lanes. In one example, the second and third phases are performed in software, and may include testing a “victim” lane, with adjacent “aggressor” lanes having a complementary bit pattern.

公开(公告)号：US20190238179A1

公开(公告)日：2019-08-01

申请号：US15761408

申请日：2015-09-26

Applicant: Intel Corporation

Inventor： Venkatraman Iyer ,  Lip Khoon Teh ,  Mahesh Wagh ,  Zuoguo Wu ,  Azydee Hamid ,  Gerald S. Pasdast

IPC: H04B3/40 ,  H04L25/03 ,  G06F13/20

CPC classification number: H04B3/40 ,  G06F13/20 ,  G06F13/40 ,  H04L25/03006 ,  H04L2025/0377

Abstract: One or more link training signals are received, including instances of a link training pattern, on a plurality of lanes of a physical link that includes at least one valid lane and a plurality of data lanes. The plurality of lanes are trained together using the link training signals to synchronize sampling of the valid lane with sampling of the plurality of data lanes. An active link state is entered and a valid signal received on the valid lane during the active link state. The valid signal includes a signal held at a value for a defined first duration and indicates that data is to be received on the plurality of data lanes in a second defined duration subsequent to the first duration. The data is to be received, during the active link state, on the plurality of data lanes during the second defined duration.

公开(公告)号：US10191877B2

公开(公告)日：2019-01-29

申请号：US14978179

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： David J. Harriman ,  Manjari Kulkarni ,  Akshay G. Pethe ,  Sean O. Stalley ,  Mahesh Wagh ,  Debendra Das Sharma

IPC: G06F13/40 ,  G06F13/36 ,  G06F13/42

Abstract: An interconnect switch is provided including switching logic executable to facilitate a Peripheral Component Interconnect Express (PCIe)-based interconnect, and further including a control host embedded in the switch to provide one or more enhanced routing capabilities. The control host includes a processor device, memory, and software executable by the processor device to process traffic received at one or more ports of the switch to redirect at least a portion of the traffic to provide the one or more enhanced routing capabilities.

公开(公告)号：US20180300275A1

公开(公告)日：2018-10-18

申请号：US15821492

申请日：2017-11-22

Applicant: Intel Corporation

Inventor： Zuoguo J. Wu ,  Mahesh Wagh ,  Debendra Das Sharma ,  Gerald S. Pasdast ,  Ananthan Ayyasamy ,  Xiaobei Li ,  Robert G. Blankenship ,  Robert J. Safranek

IPC: G06F13/40 ,  G06F1/10

CPC classification number: G06F13/4022 ,  G06F1/10 ,  G06F13/124 ,  G06F13/4273 ,  G06F13/4282 ,  G06F15/173 ,  Y02D10/14 ,  Y02D10/151

Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

公开(公告)号：US09946676B2

公开(公告)日：2018-04-17

申请号：US14669975

申请日：2015-03-26

Applicant: Intel Corporation

Inventor： Mahesh Wagh ,  Zuoguo Wu ,  Venkatraman Iyer ,  Gerald S. Pasdast ,  Mark S. Birrittella ,  Ishwar Agarwal ,  Lip Khoon Teh ,  Su Wei Lim ,  Anoop Kumar Upadhyay

IPC: G06F17/50 ,  G06F13/40 ,  G06F13/36

CPC classification number: G06F13/4022 ,  G06F13/36 ,  G06F13/4068

Abstract: A system-on-a-chip, such as a logical PHY, may be divided into hard IP blocks with fixed routing, and soft IP blocks with flexible routing. Each hard IP block may provide a fixed number of lanes. Using p hard IP blocks, where each block provides n data lanes, h=n*p total hard IP data lanes are provided. Where the system design calls for k total data lanes, it is possible that k≠h, so that ┌k/n┐ hard IP blocks provide h=n*p available hard IP data lanes. In that case, h−k lanes may be disabled. In cases where lane reversals occur, such as between hard IP and soft IP, bowtie routing may be avoided by the use of a multiplexer-like programmable switch within the soft IP.

公开(公告)号：US20180095923A1

公开(公告)日：2018-04-05

申请号：US15283309

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Venkatraman Iyer ,  Mahesh Wagh ,  William R. Halleck ,  Rahul R. Shah

IPC: G06F13/40 ,  G06F13/36 ,  G06F13/42

CPC classification number: G06F13/4068 ,  G06F13/36 ,  G06F13/4022 ,  G06F13/4027 ,  G06F13/4265 ,  G11C27/04

Abstract: An interface adapter to identify a first ready signal from a first link layer-to-physical layer (LL-PHY) interface of a first communication protocol indicating readiness of a physical layer of the first protocol to accept link layer data. The interface adapter generates a second ready signal compatible with a second LL-PHY interface of a second communication protocol to cause link layer data to be sent from a link layer of the second communication protocol according to a predefined delay. A third ready signal is generated compatible with the first LL-PHY interface to indicate to the physical layer of the first communication protocol that the link layer data is to be sent. The interface adapter uses a shift register to cause the link layer data to be passed to the physical layer according to the predefined delay.

公开(公告)号：US20160170914A1

公开(公告)日：2016-06-16

申请号：US14986268

申请日：2015-12-31

Applicant: Intel Corporation

Inventor： Akshay G. Pethe ,  David J. Harriman ,  Mahesh Wagh ,  Abdul Hawk Ismail

IPC: G06F13/10 ,  G06F1/26 ,  G06F13/42

CPC classification number: G06F13/102 ,  G06F1/266 ,  G06F1/3203 ,  G06F13/287 ,  G06F13/387 ,  G06F13/4022 ,  G06F13/4221 ,  G06F13/4282

Abstract: Techniques for transmitted data through a USB port using a PCIe protocol are described herein. In one example, an apparatus includes a host controller, a root port, a multiplexor coupled to the host controller and the root port and a power delivery module. The power delivery module and the multiplexor can transmit and receive a request via a multimode input/output (I/O) interface and the power delivery module can detect a presence of an external device in response to the external device being coupled to the multimode I/O interface. The power delivery module can also send a first request to the external device to discover a vendor identifier of the external device, send a second request to discover at least one alternate mode supported by the external device, and send a third request to enable data transfer via the protocol.

Abstract translation: 本文描述了通过使用PCIe协议的USB端口传输的数据的技术。 在一个示例中，设备包括主机控制器，根端口，耦合到主控制器和根端口的多路复用器以及电源传递模块。 功率传递模块和多路复用器可以经由多模式输入/输出（I / O）接口发送和接收请求，并且功率传递模块可以响应外部设备耦合到多模I，检测外部设备的存在 / O接口。 电力传递模块还可以向外部设备发送第一请求以发现外部设备的供应商标识符，发送第二请求以发现由外部设备支持的至少一个替代模式，并且发送第三请求以启用数据传输 通过协议。

公开(公告)号：US20160116959A1

公开(公告)日：2016-04-28

申请号：US14986580

申请日：2015-12-31

Applicant: Intel Corporation

Inventor： Mahesh Wagh ,  Lily Pao Looi

IPC: G06F1/32 ,  G06F9/44

CPC classification number: G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/325 ,  G06F1/3275 ,  G06F1/3278 ,  G06F1/3287 ,  G06F9/4418 ,  G06F13/4265 ,  G06F13/4282 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D10/44

Abstract: Methods and apparatus relating to device power management state transition latency advertisement for faster boot time are described. In some embodiments, a storage unit stores a value corresponding to a requisite transition delay period for a first agent to exit from a low power consumption state. The first agent writes the value to the storage unit and a second agent waits for the requisite transition delay period (after the first agent initiates its exit from the low power consumption state) before the second agent attempts to communicate with the first agent via a link. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了与设备电源管理状态转换延迟广告相关的方法和装置，用于更快的启动时间。 在一些实施例中，存储单元存储对应于第一代理从低功耗状态退出的必要的转换延迟周期的值。 第一代理人将该值写入存储单元，并且第二代理程序在第二代理程序尝试通过链路与第一代理进行通信之前，等待必要的转换延迟周期（在第一代理程序从低功耗状态退出之后） 。 还公开并要求保护其他实施例。

公开(公告)号：US20160110309A1

公开(公告)日：2016-04-21

申请号：US14986573

申请日：2015-12-31

Applicant: Intel Corporation

Inventor： Mahesh Wagh ,  Lily Pao Looi

IPC: G06F13/42

CPC classification number: G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/325 ,  G06F1/3275 ,  G06F1/3278 ,  G06F1/3287 ,  G06F9/4418 ,  G06F13/4265 ,  G06F13/4282 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D10/44

Abstract: Methods and apparatus relating to device power management state transition latency advertisement for faster boot time are described. In some embodiments, a storage unit stores a value corresponding to a requisite transition delay period for a first agent to exit from a low power consumption state. The first agent writes the value to the storage unit and a second agent waits for the requisite transition delay period (after the first agent initiates its exit from the low power consumption state) before the second agent attempts to communicate with the first agent via a link. Other embodiments are also disclosed and claimed.

公开(公告)号：US09026682B2

公开(公告)日：2015-05-05

申请号：US13713635

申请日：2012-12-13

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC: G06F3/00 ,  G06F12/08 ,  G06F1/32 ,  H04L12/66 ,  G06F13/40 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract translation: 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。