公开(公告)号：US20210134802A1

公开(公告)日：2021-05-06

申请号：US16669599

申请日：2019-10-31

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mauro J. Kobrinsky ,  Abhishek A. Sharma ,  Tahir Ghani ,  Doug Ingerly ,  Rajesh Kumar

IPC: H01L27/108

Abstract: Described herein are IC devices that include transistors with contacts to one of the source/drain (S/D) regions being on the front side of the transistors and contacts to the other one of the S/D regions being on the back side of the transistors (i.e., “back-side contacts”). Using transistors with one front-side and one back-side S/D contacts provides advantages and enables unique architectures that were not possible with conventional front-end-of-line transistors with both S/D contacts being on one side.

公开(公告)号：US10985184B2

公开(公告)日：2021-04-20

申请号：US15470832

申请日：2017-03-27

Applicant: INTEL CORPORATION

Inventor： Martin D. Giles ,  Tahir Ghani

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L29/165 ,  H01L21/02

Abstract: Embodiments of the present disclosure relate to non-planar semiconductor device structures having fins. In one embodiment, a semiconductor device includes a substrate, silicon fins positioned on the substrate, and a germanium layer that is epitaxially grown on an upper region of the silicon fins with the silicon fins and the germanium layer forming a body of the semiconductor device.

公开(公告)号：US10811595B2

公开(公告)日：2020-10-20

申请号：US16073687

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： Kevin J. Lee ,  Oleg Golonzka ,  Tahir Ghani ,  Ruth A. Brain ,  Yih Wang

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01L43/14

Abstract: Techniques are disclosed for forming a logic device including integrated spin-transfer torque magnetoresistive random-access memory (STT-MRAM). In accordance with some embodiments, one or more magnetic tunnel junction (MTJ) devices may be formed within a given back-end-of-line (BEOL) interconnect layer of a host logic device. A given MTJ device may be formed, in accordance with some embodiments, over an electrically conductive layer configured to serve as a pedestal layer for the MTJ's constituent magnetic and insulator layers. In accordance with some embodiments, one or more conformal spacer layers may be formed over sidewalls of a given MTJ device and attendant pedestal layer, providing protection from oxidation and corrosion. A given MTJ device may be electrically coupled with an underlying interconnect or other electrically conductive feature, for example, by another intervening electrically conductive layer configured to serve as a thin via, in accordance with some embodiments.

公开(公告)号：US10797150B2

公开(公告)日：2020-10-06

申请号：US15770468

申请日：2015-12-17

Applicant: Intel Corporation

Inventor： Sean T. Ma ,  Willy Rachmady ,  Matthew V. Metz ,  Chandra S. Mohapatra ,  Gilbert Dewey ,  Nadia M. Rahhal-Orabi ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/00 ,  H01L29/49 ,  H01L29/78 ,  H01L29/10 ,  H01L21/28 ,  H01L29/205 ,  H01L29/66

Abstract: An apparatus including a non-planar body on a substrate, the body including a channel on a blocking material, and a gate stack on the body, the gate stack including a first gate electrode material including a first work function disposed on the channel material and a second gate electrode material including a second work function different from the first work function disposed on the channel material and on the blocking material. A method including forming a non-planar body on a substrate, the non-planar body including a channel on a blocking material, and forming a gate stack on the body, the gate stack including a first gate electrode material including a first work function disposed on the channel and a second gate electrode material including a second work function different from the first work function disposed on the channel and on the blocking material.

公开(公告)号：US10790354B2

公开(公告)日：2020-09-29

申请号：US16398995

申请日：2019-04-30

Applicant: Intel Corporation

Inventor： Milton Clair Webb ,  Mark Bohr ,  Tahir Ghani ,  Szuya S. Liao

IPC: H01L29/76 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/092 ,  H01L29/417 ,  H01L21/8234

Abstract: Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.

公开(公告)号：US10777656B2

公开(公告)日：2020-09-15

申请号：US16577993

申请日：2019-09-20

Applicant: Intel Corporation

Inventor： Tahir Ghani ,  Byron Ho ,  Curtis W. Ward ,  Michael L. Hattendorf ,  Christopher P. Auth

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/417 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11 ,  H01L49/02 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L21/02 ,  H01L29/167 ,  H01L23/00

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin, the first end of the first portion of the fin having a depth. A gate structure is over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin. A second isolation structure is over a second end of a first portion of the fin, the second end of the first portion of the fin having a depth different than the depth of the first end of the first portion of the fin.

公开(公告)号：US10770458B2

公开(公告)日：2020-09-08

申请号：US15754709

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： Rishabh Mehandru ,  Tahir Ghani ,  Szuya S. Liao ,  Seiyon Kim

IPC: H01L29/423 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/51 ,  H01L29/775 ,  H01L29/78 ,  B82Y10/00 ,  H01L29/786 ,  B82Y40/00

Abstract: Techniques are disclosed for forming nanowire transistor architectures in which the presence of gate material between neighboring nanowires is eliminated or otherwise reduced. In some examples, neighboring nanowires can be formed sufficiently proximate one another such that their respective gate dielectric layers are either: (1) just in contact with one another (e.g., are contiguous); or (2) merged with one another to provide a single, continuous dielectric layer shared by the neighboring nanowires. In some cases, a given gate dielectric layer may be of a multi-layer configuration, having two or more constituent dielectric layers. Thus, in some examples, the gate dielectric layers of neighboring nanowires may be formed such that one or more constituent dielectric layers are either: (1) just in contact with one another (e.g., are contiguous); or (2) merged with one another to provide a single, continuous constituent dielectric layer shared by the neighboring nanowires.

公开(公告)号：US20200279916A1

公开(公告)日：2020-09-03

申请号：US16647695

申请日：2017-12-20

Applicant: INTEL CORPORATION

Inventor： Willy Rachmady ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Nicholas G. Minutillo ,  Sean T. Ma ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Tahir Ghani ,  Gilbert Dewey

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/205 ,  H01L29/66

Abstract: A transistor includes a body of semiconductor material with a gate structure in contact with a portion of the body. A source region contacts the body adjacent the gate structure and a drain region contacts the body adjacent the gate structure such that the portion of the body is between the source region and the drain region. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).

公开(公告)号：US10749032B2

公开(公告)日：2020-08-18

申请号：US16076550

申请日：2016-03-11

Applicant: INTEL CORPORATION

Inventor： Chandra S. Mohapatra ,  Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Willy Rachmady ,  Gilbert Dewey ,  Tahir Ghani ,  Jack T. Kavalieros

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/775 ,  B82Y10/00 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8252 ,  H01L27/092 ,  H01L29/20

Abstract: Techniques are disclosed for forming transistors including one or more group III-V semiconductor material nanowires using sacrificial group IV semiconductor material layers. In some cases, the transistors may include a gate-all-around (GAA) configuration. In some cases, the techniques may include forming a replacement fin stack that includes group III-V material layer (such as indium gallium arsenide, indium arsenide, or indium antimonide) formed on a group IV material buffer layer (such as silicon, germanium, or silicon germanium), such that the group IV buffer layer can be later removed using a selective etch process to leave the group III-V material for use as a nanowire in a transistor channel. In some such cases, the group III-V material layer may be grown pseudomorphically to the underlying group IV material, so as to not form misfit dislocations. The techniques may be used to form transistors including any number of nanowires.

公开(公告)号：US20200220024A1

公开(公告)日：2020-07-09

申请号：US16640469

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Jack T. Kavalieros ,  Cory E. Weber ,  Sean T. Ma ,  Tahir Ghani ,  Shriram Shivaraman ,  Gilbert Dewey

IPC: H01L29/786 ,  H01L29/16 ,  H01L29/51 ,  H01L29/792 ,  H01L27/108

Abstract: A back-gated thin-film transistor (TFT) includes a gate electrode, a gate dielectric on the gate electrode, an active layer on the gate dielectric and having source and drain regions and a semiconductor region physically connecting the source and drain regions, a capping layer on the semiconductor region, and a charge trap layer on the capping layer. In an embodiment, a memory cell includes this back-gated TFT and a capacitor, the gate electrode being electrically connected to a wordline and the source region being electrically connected to a bitline, the capacitor having a first terminal electrically connected to the drain region, a second terminal, and a dielectric medium electrically separating the first and second terminals. In another embodiment, an embedded memory includes wordlines extending in a first direction, bitlines extending in a second direction crossing the first direction, and several such memory cells at crossing regions of the wordlines and bitlines.