中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

114 records (took 0.02 seconds)

    ReRAM materials stack for low-operating-power and high-density applications
    71.
    发明授权
    ReRAM materials stack for low-operating-power and high-density applications 有权
    ReRAM材料堆叠用于低功耗和高密度应用

    公开(公告)号：US09000407B2

    公开(公告)日：2015-04-07

    申请号：US13903656

    申请日：2013-05-28

    Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

    Inventor： Yun Wang ,  Tony P. Chiang ,  Dipankar Pramanik

    IPC: H01L45/00

    CPC classification number: H01L45/146 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/1616 ,  H01L45/1641

    Abstract: A switching element for resistive-switching memory (ReRAM) provides a controllable, consistent filament break-point at an abrupt structural discontinuity between a layer of high-k high-ionicity variable-resistance (VR) material and a layer of low-k low-ionicity VR material. The high-ionicity layer may be crystalline and the low-ionicity layer may be amorphous. The consistent break-point and characteristics of the low-ionicity layer facilitate lower-power operation. The defects (e.g., oxygen or nitrogen vacancies) that constitute the filament originate either in the high-ionicity VR layer or in a source electrode. The electrode nearest to the low-ionicity layer may be intrinsically inert or may be rendered effectively inert. Some electrodes are rendered effectively inert by the creation of the low-ionicity layer over the electrode.

    Abstract translation: 用于电阻式开关存储器（ReRAM）的开关元件在高k高离子度可变电阻（VR）材料层和低k低电平层之间突然的结构不连续性时提供可控的一致的灯丝断裂点 活性VR材料。 高离子层可以是结晶的，低离子层可以是无定形的。 低离子层的一致性断点和特性有利于低功率运行。 构成长丝的缺陷（例如，氧或氮空位）起源于高离子性VR层或源电极。 最接近低离子层的电极本质上是惰性的，或者可以有效地使其成为惰性的。 通过在电极上产生低离子层，使一些电极变得有效地是惰性的。

    Flourine-stabilized interface
    72.
    发明授权
    Flourine-stabilized interface 有权
    面粉稳定的界面

    公开(公告)号：US08921181B2

    公开(公告)日：2014-12-30

    申请号：US13728957

    申请日：2012-12-27

    Applicant: Intermolecular, Inc.

    Inventor： Dipankar Pramanik

    IPC: H01L29/66 ,  H01L21/84 ,  H01L29/40 ,  H01L29/423 ,  H01L29/786 ,  H01L21/28

    CPC classification number: H01L29/401 ,  H01L21/28176 ,  H01L21/28202 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/785 ,  H01L29/7866

    Abstract: Methods for forming an electronic device having a fluorine-stabilized semiconductor substrate surface are disclosed. In an exemplary embodiment, a layer of a high-κ dielectric material is formed together with a layer containing fluorine on a semiconductor substrate. Subsequent annealing causes the fluorine to migrate to the surface of the semiconductor (for example, silicon, germanium, or silicon-germanium). A thin interlayer of a semiconductor oxide may also be present at the semiconductor surface. The fluorine-containing layer can comprise F-containing WSix formed by ALD from WF6 and SiH4 precursor gases. A precise amount of F can be provided, sufficient to bind to substantially all of the dangling semiconductor atoms at the surface of the semiconductor substrate and sufficient to displace substantially all of the hydrogen atoms present at the surface of the semiconductor substrate.

    Abstract translation: 公开了一种形成具有氟稳定的半导体衬底表面的电子器件的方法。 在一个示例性实施例中， 介电材料与半导体衬底上含氟层一起形成。 随后的退火使氟迁移到半导体的表面（例如，硅，锗或硅 - 锗）。 半导体氧化物的薄中间层也可以存在于半导体表面。 含氟层可以包含由WF6的ALD和SiH 4前体气体形成的含F的WSix。 可以提供精确量的F，其足以与半导体衬底的表面上的基本上所有的悬空半导体原子结合，并且足以使基本上位于半导体衬底的表面处的所有氢原子置换。

    Controlling ReRam forming voltage with doping
    74.
    发明授权
    Controlling ReRam forming voltage with doping 有权
    用掺杂控制ReRam形成电压

    公开(公告)号：US08907313B2

    公开(公告)日：2014-12-09

    申请号：US13719051

    申请日：2012-12-18

    Applicant: Intermolecular, Inc.

    Inventor： Sergey Barabash ,  Charlene Chen ,  Dipankar Pramanik

    IPC: H01L29/02 ,  H01L45/00

    CPC classification number: H01L45/1616 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1641

    Abstract: An internal electrical field in a resistive memory element can be formed to reduce the forming voltage. The internal electric field can be formed by incorporating one or more charged layers within the switching dielectric layer of the resistive memory element. The charged layers can include adjacent charge layers to form dipole layers. The charged layers can be formed at or near the interface of the switching dielectric layer with an electrode layer. Further, the charged layer can be oriented with lower valence substitution side towards lower work function electrode, and higher valence substitution side towards higher work function electrode.

    Abstract translation: 可以形成电阻式存储元件中的内部电场以降低成形电压。 可以通过在电阻式存储元件的开关电介质层内并入一个或多个带电层来形成内部电场。 带电层可以包括相邻的电荷层以形成偶极层。 带电层可以在开关电介质层的界面处或附近形成电极层。 此外，带电层可以朝向较低功函电极的较低价取代面取向，而朝较高功函电极取向较高的取代价。

    Creating An Embedded ReRam Memory From A High-K Metal Gate Transistor Structure
    76.
    发明申请
    Creating An Embedded ReRam Memory From A High-K Metal Gate Transistor Structure 审中-公开
    从高K金属栅晶体管结构创建嵌入式ReRam存储器

    公开(公告)号：US20140319449A1

    公开(公告)日：2014-10-30

    申请号：US14325580

    申请日：2014-07-08

    Applicant: Intermolecular Inc.

    Inventor： Dipankar Pramanik ,  Tony P. Chiang ,  David E Lazovsky

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L45/1658 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1683

    Abstract: An embodiment of the present invention sets forth an embedded resistive memory cell that includes a first stack of deposited layers, a second stack of deposited layers, a first electrode disposed under a first portion of the first stack, and a second electrode disposed under a second portion of the first stack and extending from under the second portion of the first stack to under the second stack. The second electrode is disposed proximate to the first electrode within the embedded resistive memory cell. The first stack of deposited layers includes a dielectric layer, a high-k dielectric layer disposed above the dielectric layer, and a metal layer disposed above the high-k dielectric layer. The second stack of deposited layers includes a high-k dielectric layer formed simultaneously with the high-k dielectric layer included in the first stack, and a metal layer disposed above the high-k dielectric layer.

    Abstract translation: 本发明的实施例提出了一种嵌入式电阻式存储单元，其包括沉积层的第一堆叠，沉积层的第二堆叠，设置在第一堆叠的第一部分下方的第一电极和设置在第二堆叠下的第二电极的第二电极 第一堆叠的部分并且从第一堆叠的第二部分下方延伸到第二堆叠下方。 第二电极设置在嵌入式电阻式存储单元内靠近第一电极。 第一堆沉积层包括介电层，设置在电介质层上方的高k电介质层和设置在高k电介质层上方的金属层。 第二层沉积层包括与包含在第一堆叠中的高k电介质层同时形成的高k电介质层和设置在高k电介质层上方的金属层。

    Memory Device Having An Integrated Two-Terminal Current Limiting Resistor
    78.
    发明申请
    Memory Device Having An Integrated Two-Terminal Current Limiting Resistor 有权
    具有集成两端限流电阻的存储器件

    公开(公告)号：US20140299834A1

    公开(公告)日：2014-10-09

    申请号：US14288003

    申请日：2014-05-27

    Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

    Inventor： Dipankar Pramanik ,  Tony P. Chiang ,  Mankoo Lee

    IPC: H01L45/00

    CPC classification number: H01L45/14 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16

    Abstract: A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.

    Abstract translation: 提供了并入电阻式开关存储单元或装置中以形成具有改进的器件性能和寿命的存储器件的电阻器结构。 电阻器结构可以是设计成减小流过存储器件的最大电流的两端结构。 还提供了一种用于制造这种存储器件的方法。 该方法包括沉积电阻器结构并沉积存储器件的电阻式开关存储单元的可变电阻层，其中电阻器结构与可变电阻层串联设置以限制存储器件的开关电流。 电阻器结构的结合对于获得满足各种类型的存储器件的开关规范的期望的器件开关电流水平是非常有用的。 存储器件可以形成为可用于各种电子器件的大容量非易失性存储器集成电路的一部分。

    Ultrathin Coating for One Way Mirror Applications
    79.
    发明申请
    Ultrathin Coating for One Way Mirror Applications 审中-公开
    用于单向镜应用的超薄涂层

    公开(公告)号：US20140268377A1

    公开(公告)日：2014-09-18

    申请号：US14105118

    申请日：2013-12-12

    Applicant: Intermolecular, Inc.

    Inventor： Xuena Zhang ,  Dipankar Pramanik

    IPC: G02B5/08 ,  G02B1/10

    CPC classification number: G02B1/105 ,  G02B1/14 ,  G02B5/0858

    Abstract: Systems and methods for improving the performance of one way mirror applications are disclosed. Methods consistent with the present disclosure include introducing a glass substrate into a processing chamber. The processing chamber comprises a sputter target assembly disposed over the substrate. Next, depositing metal silicide material within a plurality of site-isolated regions on the substrate to form a metal silicide coating within each region. Notably, each metal silicide coating has a thickness between 0.001 and 0.5 microns. Finally, evaluating results of the metal silicide coating formed within the plurality of site-isolated regions.

    Abstract translation: 公开了用于改善单向镜应用的性能的系统和方法。 与本公开一致的方法包括将玻璃基板引入处理室。 处理室包括设置在衬底上的溅射靶组件。 接下来，在衬底上的多个位置隔离区域内沉积金属硅化物材料，以在每个区域内形成金属硅化物涂层。 值得注意的是，每个金属硅化物涂层的厚度为0.001至0.5微米。 最后，评估在多个位置隔离区域内形成的金属硅化物涂层的结果。

Patent Agency Ranking