公开(公告)号：US20060119384A1

公开(公告)日：2006-06-08

申请号：US11003586

申请日：2004-12-02

申请人： Rafael Camarota ,  Irfan Rahim ,  Boon Ang ,  Thow Chong

发明人： Rafael Camarota ,  Irfan Rahim ,  Boon Ang ,  Thow Chong

IPC分类号： H03K19/173

CPC分类号： G06F15/7867 ,  H03K19/17732 ,  H03K19/1776 ,  H03K19/17768 ,  H03K19/17772 ,  H03K19/17776

摘要： Techniques for combining volatile and non-volatile programmable logic into one integrated circuit (IC) are provided. An IC is segregated into two portions. A first block of programmable logic is configured by bits stored in on-chip non-volatile memory. A second block of programmable logic is configured by bits stored in off-chip memory. The function of IO banks on the IC is multiplexed between the two logic blocks of the IC. The programmable logic in the first block can be configured and fully functional in a fraction of the time that the programmable logic in the second block can be configured. The programmable logic in the first block can configure fast enough and have enough independence to assist in the configuration of the second block. The non-volatile memory can also provide security features to a user design, such as encryption.

摘要翻译： 提供了将易失性和非易失性可编程逻辑组合到一个集成电路（IC）中的技术。 IC分为两部分。 可编程逻辑的第一块由存储在片上非易失性存储器中的位来配置。 可编程逻辑的第二块由存储在片外存储器中的位配置。 IC上的IO组的功能在IC的两个逻辑块之间复用。 第一块中的可编程逻辑可以在可配置第二块中的可编程逻辑的几分之一时间内配置和完全运行。 第一块中的可编程逻辑可以配置得足够快，并具有足够的独立性来辅助第二块的配置。 非易失性存储器还可以为诸如加密的用户设计提供安全特征。

公开(公告)号：US06773987B1

公开(公告)日：2004-08-10

申请号：US10156514

申请日：2002-05-28

申请人： Irfan Rahim ,  Fangyun Richter

发明人： Irfan Rahim ,  Fangyun Richter

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/66825

摘要： A method of fabricating a non-volatile memory cell on a semiconductor substrate is disclosed. An area of a first region of the semiconductor substrate designated for a layer of floating polysilicon is blocked while a second region of the semiconductor substrate designated for a layer of non-floating polysilicon is exposed. Exposed regions of the semiconductor substrate are doped with charges.

摘要翻译： 公开了一种在半导体衬底上制造非易失性存储单元的方法。 指定用于浮动多晶硅层的半导体衬底的第一区域的区域被封闭，而指定用于非浮动多晶硅层的第二半导体衬底的区域被暴露。 半导体衬底的暴露区域掺杂有电荷。

公开(公告)号：US06476635B1

公开(公告)日：2002-11-05

申请号：US09604992

申请日：2000-06-28

申请人： Irfan Rahim ,  John E. Berg

发明人： Irfan Rahim ,  John E. Berg

IPC分类号： H03K19177

CPC分类号： H03K19/17748 ,  H03K19/1778 ,  H03K19/17792

摘要： A layout architecture for a programmable logic device comprising one or more adjacent metal lines, a first circuit, and a second circuit. The one or more adjacent metal lines may each comprise a critical path. The first circuit may be configured to present an input signal to each of the one or more adjacent metal lines in response to a configuration signal. The second circuit may be configured to (i) receive a signal from at least one of the one or more adjacent metal lines selected in response to the configuration signal and (ii) generate an output signal in response to the received signal.

摘要翻译： 一种用于包括一个或多个相邻金属线，第一电路和第二电路的可编程逻辑器件的布局架构。 一个或多个相邻的金属线可以各自包括关键路径。 第一电路可以被配置为响应于配置信号向一个或多个相邻金属线中的每一个呈现输入信号。 第二电路可以被配置为（i）从响应于配置信号选择的一个或多个相邻金属线中的至少一个接收信号，以及（ii）响应于接收到的信号产生输出信号。

公开(公告)号：US6124157A

公开(公告)日：2000-09-26

申请号：US45294

申请日：1998-03-20

申请人： Irfan Rahim

发明人： Irfan Rahim

IPC分类号： H01L21/762 ,  H01L21/8247 ,  H01L27/105 ,  H01L21/8238

CPC分类号： H01L27/11526 ,  H01L21/76202 ,  H01L27/105 ,  H01L27/11546

摘要： A method of forming non-volatile memory (e.g., an EEPROM device) and a CMOS device (e.g., a RAM), on a single die or chip, and a structure formed by the method. In one embodiment, the control gate of the storage transistor as well as the isolation gate of the isolation transistor may be formed during the same manufacturing process step, and thus may be formed of the same gate poly material and may have similar thickness.

摘要翻译： 在单个芯片或芯片上形成非易失性存储器（例如，EEPROM器件）和CMOS器件（例如，RAM）的方法以及通过该方法形成的结构。 在一个实施例中，存储晶体管的控制栅极以及隔离晶体管的隔离栅极可以在相同的制造工艺步骤期间形成，并且因此可以由相同的栅极聚合材料形成并且可以具有类似的厚度。

公开(公告)号：US08921170B1

公开(公告)日：2014-12-30

申请号：US13408959

申请日：2012-02-29

申请人： Jun Liu ,  Albert Ratnakumar ,  Mark T. Chan ,  Irfan Rahim

发明人： Jun Liu ,  Albert Ratnakumar ,  Mark T. Chan ,  Irfan Rahim

IPC分类号： H01L21/338

CPC分类号： H01L21/823418 ,  H01L21/324 ,  H01L21/823814 ,  H01L27/082 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66659

摘要： Asymmetric transistors such as asymmetric pass transistors may be formed on an integrated circuit. The asymmetric transistors may have gate structures. Symmetric pocket implants may be formed in source-drains on opposing sides of each transistor gate structure. Selective heating may be used to asymmetrically diffuse the implants. Selective heating may be implemented by patterning the gate structures on a semiconductor substrate so that the spacing between adjacent gate structures varies. A given gate structure may be located between first and second adjacent gate structures spaced at different respective distances from the given gate structure. A larger gate structure spacing leads to a greater substrate temperature rise than a smaller gate structure spacing. The pocket implant diffuses more in portions of the substrate with the greater temperature rise, producing asymmetric transistors. Asymmetric pass transistors may be controlled by static control signals from memory elements to implement circuits such as programmable multiplexers.

摘要翻译： 不对称晶体管，例如不对称传输晶体管可以形成在集成电路上。 不对称晶体管可以具有栅极结构。 可以在每个晶体管栅极结构的相对侧上的源极漏极中形成对称的袋状植入物。 选择性加热可用于不对称地扩散植入物。 可以通过在半导体衬底上图案化栅极结构来实现选择性加热，使得相邻栅极结构之间的间隔变化。 给定的栅极结构可以位于与给定栅极结构不同的相应距离处间隔开的第一和第二相邻栅极结构之间。 较大的栅极结构间隔导致比较小栅极结构间隔更大的衬底温度升高。 在较大的温度上升的情况下，口袋植入物在衬底的部分扩散，产生不对称晶体管。 不对称传输晶体管可以由来自存储器元件的静态控制信号来控制，以实现诸如可编程多路复用器之类的电路。

公开(公告)号：US08804407B1

公开(公告)日：2014-08-12

申请号：US13181219

申请日：2011-07-12

申请人： Jun Liu ,  Albert Ratnakumar ,  Irfan Rahim ,  Qi Xiang

发明人： Jun Liu ,  Albert Ratnakumar ,  Irfan Rahim ,  Qi Xiang

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  H03K2217/0054

摘要： An IC that includes a memory cell and a pass gate coupled to the memory cell, where the pass gate includes a PMOS transistor, is described. In one implementation, the PMOS transistor has a negative threshold voltage. In one implementation, the memory cell includes thick oxide transistors.

摘要翻译： 描述了包括耦合到存储器单元的存储单元和通过栅极的IC，其中栅极包括PMOS晶体管。 在一个实现中，PMOS晶体管具有负阈值电压。 在一个实现中，存储单元包括厚的氧化物晶体管。

公开(公告)号：US08704313B1

公开(公告)日：2014-04-22

申请号：US11406694

申请日：2006-04-18

申请人： Irfan Rahim ,  Cheng-Hsiung Huang

发明人： Irfan Rahim ,  Cheng-Hsiung Huang

IPC分类号： H01L29/78

CPC分类号： H01L29/7391 ,  H01L27/0255

摘要： An electrostatic discharge (ESD) protection structure comprising a polysilicon gate on an insulating layer on a substrate, said gate having first and second sides, a first heavily doped P-region in the substrate on the first side of the gate, a first heavily doped N-region in the substrate on the second side of the gate, and a shallow trench isolation isolating said first P-region and said first N-region from other structures in the substrate. In a first embodiment, the heavily doped regions are formed in a well having opposite conductivity to that of the substrate and a diode is formed at a PN junction between one of the heavily doped regions and the well. To minimize capacitance between the well and the substrate, the substrate is doped at a level of native doping and the well is isolated so that no other wells or heavily-doped regions are nearby in the substrate. Doping levels in the well and the dimensions of the gate are controlled to minimize on resistance (Ron) of the diode. In a second embodiment, no well is used.

摘要翻译： 一种静电放电（ESD）保护结构，包括在衬底上的绝缘层上的多晶硅栅极，所述栅极具有第一和第二侧，栅极第一侧上的衬底中的第一重掺杂P区，第一重掺杂 在栅极的第二侧的衬底中的N区，以及将衬底中的其它结构隔离所述第一P区和所述第一N区的浅沟槽隔离。 在第一实施例中，重掺杂区域形成在具有与衬底相反的导电性的阱中，并且在重掺杂区域之一和阱之间的PN结处形成二极管。 为了最小化阱和衬底之间的电容，衬底以天然掺杂的水平掺杂，并且阱被隔离，使得衬底中没有其它阱或重掺杂区域在附近。 阱中的掺杂电平和栅极的尺寸被控制以使二极管的导通电阻（Ron）最小化。 在第二实施例中，不使用井。

公开(公告)号：US08542032B1

公开(公告)日：2013-09-24

申请号：US13345436

申请日：2012-01-06

申请人： Michael D. Hutton ,  Irfan Rahim

发明人： Michael D. Hutton ,  Irfan Rahim

IPC分类号： H03K19/173

CPC分类号： G06F17/5054 ,  G06F17/5031 ,  G06F17/5059 ,  G06F2217/06 ,  G06F2217/08 ,  G06F2217/82 ,  G06F2217/84 ,  H03K19/1737 ,  H03K19/17736 ,  H03K19/1776

摘要： Integrated circuits such as programmable integrated circuits may include programmable logic regions that can be configured to perform custom user functions. The programmable logic regions may produce output signals. The integrated circuit may include interconnects that route selected output signals throughout the integrated circuit. The integrated circuit may include output selection circuitry having output selection and interconnect selection stages. The output selection circuitry may be configured to select which of the output signals produced by the programmable logic regions are provided to the interconnects for routing. The interconnect selection stage may be formed using multiplexing circuits or tristate drivers. Logic design system computing equipment may be used to generate configuration data that can be used to program the output selection circuitry to reduce crosstalk by routing signals away from critical interconnects or by double-driving critical interconnects.

摘要翻译： 诸如可编程集成电路的集成电路可以包括可被配置为执行定制用户功能的可编程逻辑区域。 可编程逻辑区域可以产生输出信号。 集成电路可以包括在整个集成电路中路由选择的输出信号的互连。 集成电路可以包括具有输出选择和互连选择阶段的输出选择电路。 输出选择电路可以被配置为选择由可编程逻辑区域产生的输出信号中的哪一个被提供给用于路由的互连。 可以使用多路复用电路或三态驱动器来形成互连选择级。 逻辑设计系统计算设备可用于产生可用于对输出选择电路编程的配置数据，以通过将信号路由远离关键互连或通过双重驱动关键互连来减少串扰。

公开(公告)号：US08138797B1

公开(公告)日：2012-03-20

申请号：US12790660

申请日：2010-05-28

申请人： Jun Liu ,  Albert Ratnakumar ,  Mark T. Chan ,  Irfan Rahim

发明人： Jun Liu ,  Albert Ratnakumar ,  Mark T. Chan ,  Irfan Rahim

IPC分类号： H01L25/00 ,  H03K19/00

CPC分类号： H01L21/823418 ,  H01L21/324 ,  H01L21/823814 ,  H01L27/082 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66659

摘要： Asymmetric transistors such as asymmetric pass transistors may be formed on an integrated circuit. The asymmetric transistors may have gate structures. Symmetric pocket implants may be formed in source-drains on opposing sides of each transistor gate structure. Selective heating may be used to asymmetrically diffuse the implants. Selective heating may be implemented by patterning the gate structures on a semiconductor substrate so that the spacing between adjacent gate structures varies. A given gate structure may be located between first and second adjacent gate structures spaced at different respective distances from the given gate structure. A larger gate structure spacing leads to a greater substrate temperature rise than a smaller gate structure spacing. The pocket implant diffuses more in portions of the substrate with the greater temperature rise, producing asymmetric transistors. Asymmetric pass transistors may be controlled by static control signals from memory elements to implement circuits such as programmable multiplexers.

摘要翻译： 不对称晶体管，例如不对称传输晶体管可以形成在集成电路上。 不对称晶体管可以具有栅极结构。 可以在每个晶体管栅极结构的相对侧上的源极漏极中形成对称的袋状植入物。 选择性加热可用于不对称地扩散植入物。 可以通过在半导体衬底上图案化栅极结构来实现选择性加热，使得相邻栅极结构之间的间隔变化。 给定的栅极结构可以位于与给定栅极结构不同的相应距离处间隔开的第一和第二相邻栅极结构之间。 较大的栅极结构间隔导致比较小栅极结构间隔更大的衬底温度升高。 在较大的温度上升的情况下，口袋植入物在衬底的部分扩散，产生不对称晶体管。 不对称传输晶体管可以由来自存储器元件的静态控制信号来控制，以实现诸如可编程多路复用器之类的电路。

公开(公告)号：US07858469B1

公开(公告)日：2010-12-28

申请号：US12565855

申请日：2009-09-24

申请人： Jeffrey Watt ,  Irfan Rahim

发明人： Jeffrey Watt ,  Irfan Rahim

IPC分类号： H01L21/8234

CPC分类号： H01L27/0262 ,  H01L29/4983 ,  H01L29/66659 ,  H01L29/7835

摘要： The present invention is a trigger device useful, for example, in triggering an SCR in an ESD protection circuit. Illustratively, an NMOS trigger device comprises a gate and heavily doped P and N regions in a P-well on opposite sides of the gate. A first N type source/drain extension and a first P-type pocket region extend from the P region toward the N region with the pocket region located under the source/drain extension and extending under the gate. A second N-type source/drain extension and a second P-type pocket region extend from the N region toward the P region with the pocket region located under the source/drain extension and extending under the gate. Preferably, the gate itself is heavily doped so that one half of the gate on the side adjacent the heavily doped P region is also heavily doped with dopants of P-type conductivity and the other half of the gate on the side adjacent the heavily doped N region is also heavily doped with dopants of N-type conductivity. Doping the gate increases the threshold voltage by about one Volt due to an increase in the work function on the source side of the gate.

摘要翻译： 本发明是一种触发装置，例如用于触发ESD保护电路中的SCR。 说明性地，NMOS触发器件包括在栅极的相对侧上的P阱中的栅极和重掺杂P和N区。 第一N型源极/漏极延伸部分和第一P型凹槽区域从P区域朝向N区域延伸，其中凹部区域位于源极/漏极延伸部下方并在栅极下方延伸。 第二N型源极/漏极延伸部分和第二P型凹槽区域从N区域延伸到P区域，其中该凹陷区域位于源极/漏极延伸部分下方并在栅极之下延伸。 优选地，栅极本身是重掺杂的，使得与重掺杂P区相邻的一侧的栅极的一半也被P型导电性的掺杂剂重掺杂，并且与重掺杂N相邻的一侧栅极的另一半 区域也被N型导电性的掺杂剂重掺杂。 由于栅极的源极侧的功函数增加，掺杂栅极将阈值电压提高约1伏特。