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97 条记录 (耗时 0.041 秒)

    Formation of through via before contact processing
    73.
    发明授权
    Formation of through via before contact processing 有权
    在联系处理之前形成通孔

    公开(公告)号：US09209157B2

    公开(公告)日：2015-12-08

    申请号：US13074883

    申请日：2011-03-29

    申请人： Wen-Chih Chiou ,  Chen-Hua Yu ,  Weng-Jin Wu

    发明人： Wen-Chih Chiou ,  Chen-Hua Yu ,  Weng-Jin Wu

    IPC分类号： H01L21/44 ,  H01L25/065 ,  H01L21/768 ,  H01L23/48 ,  H01L25/00

    CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541

    摘要： The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to contact or metallization processing. Contacts and bonding pads may then be fabricated after the TSVs are already in place, which allows the TSV to be more dense and allows more freedom in the overall TSV design. By providing a denser connection between TSVs and bonding pads, individual wafers and dies may be bonded directly at the bonding pads. The conductive bonding material, thus, maintains an electrical connection to the TSVs and other IC components through the bonding pads.

    摘要翻译： 描述了在集成电路（IC）管芯或晶片中形成通孔硅通孔（TSV），其中在接触或金属化处理之前的集成工艺中形成TSV。 然后可以在TSV已经就位之后制造触点和接合焊盘，这允许TSV更致密并且允许TSV设计中的更多自由度。 通过在TSV和接合焊盘之间提供更密集的连接，单个晶片和管芯可以直接接合在接合焊盘处。 因此，导电接合材料通过接合焊盘保持与TSV和其它IC部件的电连接。

    Stacked structures and methods of forming stacked structures
    74.
    发明授权
    Stacked structures and methods of forming stacked structures 有权
    堆叠结构和形成堆叠结构的方法

    公开(公告)号：US08736039B2

    公开(公告)日：2014-05-27

    申请号：US11539481

    申请日：2006-10-06

    申请人： Weng-Jin Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

    发明人： Weng-Jin Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

    IPC分类号： H01L23/22

    CPC分类号： H01L21/78 ,  H01L23/585 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A stacked structure includes a first die bonded over a second die. The first die has a first die area defined over a first surface. At least one first protective structure is formed over the first surface, around the first die area. At least one side of the first protective structure has at least one first extrusion part extending across a first scribe line around the protective structure. The second die has a second die area defined over a second surface. At least one second protective structure is formed over the second surface, around the second die area. At least one side of the second protective structure has at least one second extrusion part extending across a second scribe line around the protective structure, wherein the first extrusion part is connected with the second extrusion part.

    摘要翻译： 层叠结构包括在第二管芯上结合的第一管芯。 第一管芯具有限定在第一表面上的第一管芯区域。 在第一表面，围绕第一模具区域形成至少一个第一保护结构。 第一保护结构的至少一侧具有至少一个在保护结构周围延伸穿过第一划线的第一挤压部分。 第二模具具有限定在第二表面上的第二模具区域。 在第二表面上围绕第二管芯区域形成至少一个第二保护结构。 第二保护结构的至少一侧具有至少一个在保护结构周围延伸穿过第二划线的第二挤压部分，其中第一挤压部分与第二挤压部分连接。

    Formation of Through Via before Contact Processing
    77.
    发明申请
    Formation of Through Via before Contact Processing 审中-公开
    联络处理前通过形成

    公开(公告)号：US20110177655A1

    公开(公告)日：2011-07-21

    申请号：US13074883

    申请日：2011-03-29

    申请人： Wen-Chih Chiou ,  Chen-Hua Yu ,  Weng-Jin Wu

    发明人： Wen-Chih Chiou ,  Chen-Hua Yu ,  Weng-Jin Wu

    IPC分类号： H01L21/28

    CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541

    摘要： The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to contact or metallization processing. Contacts and bonding pads may then be fabricated after the TSVs are already in place, which allows the TSV to be more dense and allows more freedom in the overall TSV design. By providing a denser connection between TSVs and bonding pads, individual wafers and dies may be bonded directly at the bonding pads. The conductive bonding material, thus, maintains an electrical connection to the TSVs and other IC components through the bonding pads.

    摘要翻译： 描述了在集成电路（IC）管芯或晶片中形成通孔硅通孔（TSV），其中在接触或金属化处理之前的集成工艺中形成TSV。 然后可以在TSV已经就位之后制造触点和接合焊盘，这允许TSV更致密并且允许TSV设计中的更多自由度。 通过在TSV和接合焊盘之间提供更密集的连接，单个晶片和管芯可以直接接合在接合焊盘处。 因此，导电接合材料通过接合焊盘保持与TSV和其它IC部件的电连接。

    High throughput die-to-wafer bonding using pre-alignment
    78.
    发明授权
    High throughput die-to-wafer bonding using pre-alignment 有权
    使用预对准的高通量晶片到晶片键合

    公开(公告)号：US07897481B2

    公开(公告)日：2011-03-01

    申请号：US12329304

    申请日：2008-12-05

    申请人： Wen-Chih Chiou ,  Weng-Jin Wu ,  Chen-Hua Yu

    发明人： Wen-Chih Chiou ,  Weng-Jin Wu ,  Chen-Hua Yu

    IPC分类号： H01L21/98

    CPC分类号： H01L25/0657 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541

    摘要： A method of forming integrated circuits includes providing a wafer that includes a plurality of dies; aligning a first top die to a first bottom die in the wafer; recording a first destination position of the first top die after the first top die is aligned to the first bottom die; bonding the first top die onto the first bottom die; calculating a second destination position of a second top die using the first destination position; moving the second top die to the second destination position; and bonding the second top die onto a second bottom die without any additional alignment action.

    摘要翻译： 一种形成集成电路的方法包括提供包括多个管芯的晶片; 将第一顶模与所述晶片中的第一底模对准; 在所述第一顶模与所述第一底模对准之后，记录所述第一顶模的第一目的位置; 将第一顶模连接到第一底模上; 使用所述第一目的地位置计算第二顶模的第二目的位置; 将第二顶部模具移动到第二目的地位置; 以及将所述第二顶模连接到第二底模上而没有任何附加的对准作用。