公开(公告)号：US08268683B2

公开(公告)日：2012-09-18

申请号：US12782859

申请日：2010-05-19

申请人： Liang-Gi Yao ,  Chun-Hu Cheng ,  Chen-Yi Lee ,  Jeff J. Xu ,  Clement Hsingjen Wann

发明人： Liang-Gi Yao ,  Chun-Hu Cheng ,  Chen-Yi Lee ,  Jeff J. Xu ,  Clement Hsingjen Wann

IPC分类号： H01L21/8249

CPC分类号： H01L29/513 ,  H01L21/02172 ,  H01L21/022 ,  H01L21/28158 ,  H01L21/28211 ,  H01L21/283 ,  H01L29/42364 ,  H01L29/517 ,  H01L29/78

摘要： A method for reducing interfacial layer (IL) thickness for high-k dielectrics and metal gate stack is provided. In one embodiment, the method includes forming an interfacial layer on a semiconductor substrate, etching back the interfacial layer, depositing a high-k dielectric material over the interfacial layer, and forming a metal gate over the high-k dielectric material. The IL can be chemical oxide, ozonated oxide, thermal oxide, or formed by ultraviolet ozone (UVO) oxidation process from chemical oxide, etc. The etching back of IL can be performed by a Diluted HF (DHF) process, a vapor HF process, or any other suitable process. The method can further include performing UV curing or low thermal budget annealing on the interfacial layer before depositing the high-k dielectric material.

摘要翻译： 提供了一种用于降低高k电介质和金属栅极叠层的界面层（IL）厚度的方法。 在一个实施例中，该方法包括在半导体衬底上形成界面层，蚀刻回界面层，在界面层上沉积高k电介质材料，以及在高k电介质材料上形成金属栅极。 IL可以是化学氧化物，臭氧化氧化物，热氧化物，或者由化学氧化物等的紫外线臭氧（UVO）氧化过程形成.II的回蚀可以通过稀释HF（DHF）工艺，蒸气HF工艺 ，或任何其他合适的过程。 该方法还可以包括在沉积高k介电材料之前在界面层上进行UV固化或低热预算退火。

公开(公告)号：US08106469B2

公开(公告)日：2012-01-31

申请号：US12687574

申请日：2010-01-14

申请人： Jeff J. Xu ,  Liang-Gi Yao ,  Ta-Ming Kuan

发明人： Jeff J. Xu ,  Liang-Gi Yao ,  Ta-Ming Kuan

IPC分类号： H01L21/02

CPC分类号： H01L21/2822 ,  H01L21/26506 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

摘要： The present disclosure provides methods and apparatus of fluorine passivation in IC device fabrication. In one embodiment, a method of fabricating a semiconductor device includes providing a substrate and passivating a surface of the substrate with a mixture of hydrofluoric acid and alcohol to form a fluorine-passivated surface. The method further includes forming a gate dielectric layer over the fluorine-passivated surface, and then forming a metal gate electrode over the gate dielectric layer. A semiconductor device fabricated by such a method is also disclosed.

摘要翻译： 本公开提供了IC器件制造中氟钝化的方法和装置。 在一个实施例中，制造半导体器件的方法包括提供衬底并用氢氟酸和醇的混合物钝化衬底的表面以形成氟钝化表面。 该方法还包括在氟钝化表面上形成栅极电介质层，然后在栅极介电层上形成金属栅电极。 还公开了通过这种方法制造的半导体器件。

公开(公告)号：US07998820B2

公开(公告)日：2011-08-16

申请号：US11835263

申请日：2007-08-07

申请人： Chen-Hua Yu ,  Liang-Gi Yao

发明人： Chen-Hua Yu ,  Liang-Gi Yao

IPC分类号： H01L21/336

CPC分类号： H01L29/517 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： A device and method of formation are provided for a high-k gate dielectric and gate electrode. The high-k dielectric material is formed, and a silicon-rich film is formed over the high-k dielectric material. The silicon-rich film is then treated through either oxidation or nitridation to reduce the Fermi-level pinning that results from both the bonding of the high-k material to the subsequent gate conductor and also from a lack of oxygen along the interface of the high-k dielectric material and the gate conductor. A conductive material is then formed over the film through a controlled process to create the gate conductor.

摘要翻译： 为高k栅极电介质和栅电极提供了一种器件和形成方法。 形成高k电介质材料，并且在高k电介质材料上形成富硅膜。 然后通过氧化或氮化处理富硅膜，以减少由高k材料与随后的栅极导体的结合以及由高k材料与后续栅极导体之间​​的缺乏导致的费米能级钉扎 -k介质材料和栅极导体。 然后通过受控的工艺在膜上形成导电材料以产生栅极导体。

公开(公告)号：US07910467B2

公开(公告)日：2011-03-22

申请号：US12355401

申请日：2009-01-16

申请人： Yu-Rung Hsu ,  Chen-Hua Yu ,  Liang-Gi Yao

发明人： Yu-Rung Hsu ,  Chen-Hua Yu ,  Liang-Gi Yao

IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/336

CPC分类号： H01L21/28176 ,  H01L21/268 ,  H01L29/4908 ,  H01L29/517

摘要： A method for fabricating a semiconductor device with improved performance is disclosed. The method comprises providing a semiconductor substrate; forming one or more gate stacks having an interfacial layer, a high-k dielectric layer, and a gate layer over the substrate; and performing at least one treatment on the interfacial layer, wherein the treatment comprises a microwave radiation treatment, an ultraviolet radiation treatment, or a combination thereof.

摘要翻译： 公开了一种制造具有改进性能的半导体器件的方法。 该方法包括提供半导体衬底; 在所述衬底上形成具有界面层，高k电介质层和栅极层的一个或多个栅极堆叠; 以及对所述界面层进行至少一种处理，其中所述处理包括微波辐射处理，紫外线辐射处理或其组合。

公开(公告)号：US20050170577A1

公开(公告)日：2005-08-04

申请号：US10769316

申请日：2004-01-30

申请人： Liang-Gi Yao ,  Tien-Chih Chang ,  CC Lin ,  Shin-Chang Chen ,  Mong-Song Liang

发明人： Liang-Gi Yao ,  Tien-Chih Chang ,  CC Lin ,  Shin-Chang Chen ,  Mong-Song Liang

IPC分类号： C30B1/00 ,  H01L21/20 ,  H01L21/338

CPC分类号： H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532

摘要： A strained silicon layer fabrication employs a substrate having successively formed thereover: (1) a first silicon-germanium alloy material layer; (2) a first silicon layer; (3) a second silicon-germanium alloy material layer; and (4) a second silicon layer. Within the fabrication each of the first silicon-germanium alloy layer and the second silicon-germanium alloy layer is formed of a thickness less than a threshold thickness for dislocation defect formation, such as to provide attenuated dislocation defect formation within the strained silicon layer fabrication.

摘要翻译： 应变硅层制造采用在其上依次形成的基板：（1）第一硅 - 锗合金材料层; （2）第一硅层; （3）第二硅 - 锗合金材料层; 和（4）第二硅层。 在制造中，第一硅 - 锗合金层和第二硅 - 锗合金层中的每一个由低于用于位错缺陷形成的阈值厚度的厚度形成，例如在应变硅层制造中提供衰减的位错缺陷形成。

公开(公告)号：US20050093084A1

公开(公告)日：2005-05-05

申请号：US10872095

申请日：2004-06-18

申请人： Chih-Hao Wang ,  Shang-Chih Chen ,  Yen-Ping Wang ,  Hsien-Kuang Chiu ,  Liang-Gi Yao ,  Chenming Hu

发明人： Chih-Hao Wang ,  Shang-Chih Chen ,  Yen-Ping Wang ,  Hsien-Kuang Chiu ,  Liang-Gi Yao ,  Chenming Hu

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L29/51 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/1054 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833

摘要： A MOSFET includes a gate having a high-k gate dielectric on a substrate and a gate electrode on the gate dielectric. The gate dielectric protrudes beyond the gate electrode. A deep source and drain having shallow extensions are formed on either side of the gate. The deep source and drain are formed by selective in-situ doped epitaxy or by ion implantation and the extensions are formed by selective, in-situ doped epitaxy. The extensions lie beneath the gate in contact with the gate dielectric. The material of the gate dielectric and the amount of its protrusion beyond the gate electrode are selected so that epitaxial procedures and related procedures do not cause bridging between the gate electrode and the source/drain extensions. Methods of fabricating the MOSFET are described.

摘要翻译： MOSFET包括在衬底上具有高k栅极电介质的栅极和栅极电介质上的栅极电极。 栅极电介质突出超过栅电极。 在栅极的任一侧形成具有浅延伸的深源极和漏极。 深源和漏极通过选择性原位掺杂外延或通过离子注入形成，并且通过选择性原位掺杂外延形成延伸。 延伸部位于与栅极电介质接触的栅极下方。 选择栅极电介质的材料和其突出超过栅电极的量，使得外延程序和相关过程不会引起栅极电极和源极/漏极延伸部之间的桥接。 描述制造MOSFET的方法。

公开(公告)号：US5962344A

公开(公告)日：1999-10-05

申请号：US999229

申请日：1997-12-29

申请人： Yeur-Luen Tu ,  Shiang-Peng Cheng ,  Kwong-Jr Tsai ,  Liang-Gi Yao

发明人： Yeur-Luen Tu ,  Shiang-Peng Cheng ,  Kwong-Jr Tsai ,  Liang-Gi Yao

IPC分类号： H01L21/318 ,  H01L21/441

CPC分类号： H01L21/3185

摘要： A plasma treatment method used to form improved PECVD silicon nitride film passivation layers over metal interconnections on ULSI circuits is achieved. The process is carried out in a single PECVD reactor. After depositing a thin silicon oxide stress-release layer over the metal lines, a plasma-enhanced CVD silicon nitride layer is deposited, and subsequently a plasma treatment step is carried out on the silicon nitride layer. The use of a sufficiently thin silicon nitride layer eliminates photoresist trapping at the next photoresist process step that would otherwise be trapped in the voids (keyholes) that typically form in the silicon nitride passivation layer between the closely spaced metal lines, and can cause corrosion of the metal. The plasma treatment in He, Ar, or a mixture of the two, is then used to densify the silicon nitride layer and to substantially reduce pinholes that would otherwise cause interlevel metal shorts.

摘要翻译： 实现了用于在ULSI电路上的金属互连上形成改进的PECVD氮化硅膜钝化层的等离子体处理方法。 该过程在单个PECVD反应器中进行。 在金属线上沉积薄氧化硅应力释放层之后，沉积等离子体增强的CVD氮化硅层，随后在氮化硅层上进行等离子体处理步骤。 使用足够薄的氮化硅层在下一个光刻胶工艺步骤消除光致抗蚀剂捕获，否则将被捕获在通常在紧密间隔的金属线之间的氮化硅钝化层中形成的空隙（键槽）中，并且可能导致腐蚀 金属。 然后，使用He，Ar中的等离子体处理或两者的混合物来使氮化硅层致密化并且基本上减少否则将引起层间金属短路的针孔。

公开(公告)号：US08470659B2

公开(公告)日：2013-06-25

申请号：US13595599

申请日：2012-08-27

申请人： Liang-Gi Yao ,  Chun-Hu Cheng ,  Chen-Yi Lee ,  Jeff J. Xu ,  Clement Hsingjen Wann

发明人： Liang-Gi Yao ,  Chun-Hu Cheng ,  Chen-Yi Lee ,  Jeff J. Xu ,  Clement Hsingjen Wann

IPC分类号： H01L21/8249

CPC分类号： H01L29/513 ,  H01L21/02172 ,  H01L21/022 ,  H01L21/28158 ,  H01L21/28211 ,  H01L21/283 ,  H01L29/42364 ,  H01L29/517 ,  H01L29/78

摘要： This description relates to a method including forming an interfacial layer over a semiconductor substrate. The method further includes etching back the interfacial layer. The method further includes performing an ultraviolet (UV) curing process on the interfacial layer. The UV curing process includes supplying a gas flow rate ranging from 10 standard cubic centimeters per minute (sccm) to 5 standard liters per minute (slm), wherein the gas comprises inert gas, and heating the interfacial layer at a temperature less than or equal to 700° C. The method further includes depositing a high-k dielectric material over the interfacial layer.

摘要翻译： 该描述涉及包括在半导体衬底上形成界面层的方法。 该方法还包括蚀刻回界面层。 该方法还包括在界面层上进行紫外线（UV）固化过程。 UV固化方法包括将每分钟10标准立方厘米（sccm）的气体流速提供到5标准升/分钟（slm），其中气体包括惰性气体，并且在小于或等于的温度下加热界面层 至700℃。该方法还包括在界面层上沉积高k介电材料。

公开(公告)号：US08294201B2

公开(公告)日：2012-10-23

申请号：US13209493

申请日：2011-08-15

申请人： Chen-Hua Yu ,  Liang-Gi Yao

发明人： Chen-Hua Yu ,  Liang-Gi Yao

IPC分类号： H01L29/792

CPC分类号： H01L29/517 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： A device and method of formation are provided for a high-k gate dielectric and gate electrode. The high-k dielectric material is formed, and a silicon-rich film is formed over the high-k dielectric material. The silicon-rich film is then treated through either oxidation or nitridation to reduce the Fermi-level pinning that results from both the bonding of the high-k material to the subsequent gate conductor and also from a lack of oxygen along the interface of the high-k dielectric material and the gate conductor. A conductive material is then formed over the film through a controlled process to create the gate conductor.

摘要翻译： 为高k栅极电介质和栅电极提供了一种器件和形成方法。 形成高k电介质材料，并且在高k电介质材料上形成富硅膜。 然后通过氧化或氮化处理富硅膜，以减少由高k材料与随后的栅极导体的结合以及由高k材料与后续栅极导体之间​​的缺乏导致的费米能级钉扎 -k介质材料和栅极导体。 然后通过受控的工艺在膜上形成导电材料以产生栅极导体。

公开(公告)号：US20100184281A1

公开(公告)日：2010-07-22

申请号：US12355401

申请日：2009-01-16

申请人： Yu-Rung Hsu ,  Chen-Hua Yu ,  Liang-Gi Yao

发明人： Yu-Rung Hsu ,  Chen-Hua Yu ,  Liang-Gi Yao

IPC分类号： H01L21/268 ,  H01L21/336

CPC分类号： H01L21/28176 ,  H01L21/268 ,  H01L29/4908 ,  H01L29/517

摘要： A method for fabricating a semiconductor device with improved performance is disclosed. The method comprises providing a semiconductor substrate; forming one or more gate stacks having an interfacial layer, a high-k dielectric layer, and a gate layer over the substrate; and performing at least one treatment on the interfacial layer, wherein the treatment comprises a microwave radiation treatment, an ultraviolet radiation treatment, or a combination thereof.

摘要翻译： 公开了一种制造具有改进性能的半导体器件的方法。 该方法包括提供半导体衬底; 在所述衬底上形成具有界面层，高k电介质层和栅极层的一个或多个栅极堆叠; 以及对所述界面层进行至少一种处理，其中所述处理包括微波辐射处理，紫外线辐射处理或其组合。