-
公开(公告)号:US20250086443A1
公开(公告)日:2025-03-13
申请号:US18464718
申请日:2023-09-11
Applicant: Macronix International Co., Ltd.
Inventor: Feng-Min Lee , Po-Hao Tseng , Yu-Yu Lin , Ming-Hsiu Lee
IPC: G06N3/063 , G11C11/405 , G11C11/4091 , G11C11/4096 , G11C11/54
Abstract: A universal memory device includes an array of universal memory cells. Each universal memory cell includes a write transistor and a read transistor. The write transistor has a gate terminal configured to receive a gate voltage to turn on or off the write transistor, a first terminal configured to receive a write voltage, and a second terminal coupled to a gate terminal of the read transistor. The read transistor includes a charge trap layer at the gate terminal of the read transistor. The charge trap layer is configured to: be unalterable when the first write voltage is applied at the first terminal of the write transistor, and be alterable when the second write voltage is applied at the first terminal of the write transistor to change a threshold voltage of the read transistor. The second write voltage is greater than the first write voltage.
-
72.
公开(公告)号:US12142319B2
公开(公告)日:2024-11-12
申请号:US17846304
申请日:2022-06-22
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor: Po-Hao Tseng , Tian-Cih Bo , Feng-Min Lee
IPC: G11C15/04
Abstract: A hybrid type content addressable memory for implementing in-memory-search and an operation method thereof are provided. The CAM includes a plurality of CAM strings and at least one sense amplifier circuit. Each of the CAM strings includes a plurality of CAM cells. The CAM cells store a plurality of existing data. The sense amplifier circuit is connected to the CAM strings. A plurality of search data are inputted to the CAM strings. A plurality of cell matching results obtained from the CAM cells in each of the CAM strings are integrated via an AND operation to obtain a string matching result. The string matching results obtained from the CAM strings are integrated via an OR operation.
-
公开(公告)号:US12057162B2
公开(公告)日:2024-08-06
申请号:US17929318
申请日:2022-09-02
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor: Yu-Yu Lin , Feng-Min Lee
CPC classification number: G11C13/0002 , H03K19/20
Abstract: An in-memory-computing method for a memory device includes: storing weight values in cascaded computing cells each including first and second computing memory cells, wherein the first computing memory cells are cascaded in series into a first computing memory cell string and the second computing memory cells are cascaded in series into a second computing memory cell string: receiving input values by the first and the second computing memory cell strings; performing a first logic operation on the input values and the weight values by the first computing memory cell string to generate a first logic operation result, and performing a second logic operation on the input values and the weight values by the second computing memory cell string to generate a second logic operation result: and performing a third logic operation on the first and the second logic operation results to generate an output logic operation result.
-
公开(公告)号:US12020747B2
公开(公告)日:2024-06-25
申请号:US17511802
申请日:2021-10-27
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor: Po-Hao Tseng , Feng-Min Lee , Yung-Chun Li
CPC classification number: G11C11/5628 , G11C11/5671 , G11C16/10
Abstract: A non-volatile memory and a programming method thereof are provided. The programming method of the non-volatile memory includes the following steps. A coarse programming procedure is performed for programing all of a plurality of memory cells at an erase state to 2{circumflex over ( )}N−1 or 2{circumflex over ( )}N program states. N is a positive integer. A fine programming procedure is performed for pushing all of memory cells into 2{circumflex over ( )}N−1 or 2{circumflex over ( )}N verify levels.
-
公开(公告)号:US11847021B2
公开(公告)日:2023-12-19
申请号:US17680388
申请日:2022-02-25
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor: Yu-Yu Lin , Feng-Min Lee
CPC classification number: G06F11/1004 , G06F3/064 , G06F3/0619 , G06F3/0673
Abstract: An operation method of memory device, comprising: selecting a target block for performing an error correction operation; reading the target block row by row; transmitting the read data to an error correction circuit; and checking and correcting read data to generate a corrected data.
-
公开(公告)号:US11804269B2
公开(公告)日:2023-10-31
申请号:US18073366
申请日:2022-12-01
Applicant: MACRONIX International Co., Ltd.
Inventor: Feng-Min Lee , Po-Hao Tseng , Yu-Hsuan Lin , Ming-Hsiu Lee
IPC: G11C16/30 , H01L29/788 , G11C16/24 , G11C16/08 , G11C16/16 , H01L29/792 , H01L29/423 , G11C11/56 , H10B41/35 , H10B41/41 , H10B43/35 , H10B43/40
CPC classification number: G11C16/30 , G11C11/5635 , G11C11/5671 , G11C16/08 , G11C16/16 , G11C16/24 , H01L29/42392 , H01L29/7885 , H01L29/792 , H10B41/35 , H10B41/41 , H10B43/35 , H10B43/40
Abstract: A flash memory cell includes a rectifying device and a transistor. The rectifying device has an input end coupled to a bit line. The transistor has a charge storage structure. The transistor has a first end coupled to an output end of the rectifying device, the transistor has a second end coupled to a source line, and a control end of the transistor is coupled to a word line.
-
公开(公告)号:US11756620B2
公开(公告)日:2023-09-12
申请号:US17463607
申请日:2021-09-01
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor: Po-Hao Tseng , Feng-Min Lee , Ming-Hsiu Lee
CPC classification number: G11C15/046
Abstract: A memory cell for an analog content-addressable memory is provided. The memory cell includes an N-type transistor, a P-type transistor, and a current control circuit. The gate of the N-type transistor is configured to receive a first input signal. The gate of the P-type transistor is configured to receive a second input signal. The current control circuit is coupled to at least one of the N-type transistor and the P-type transistor. The current control circuit is configured to generate at least one passing current. When the input voltages of the first input signal and the second input signal are within a matching range, the N-type transistor and the P-type transistor are turned on, and the passing current is substantially a fixed current value. The matching range is related to the threshold voltages of the N-type transistor and the P-type transistor, and the fixed current value.
-
公开(公告)号:US11587617B2
公开(公告)日:2023-02-21
申请号:US17333046
申请日:2021-05-28
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor: Po-Hao Tseng , Feng-Min Lee , Ming-Hsiu Lee , Liang-Yu Chen , Yun-Yuan Wang
IPC: G11C15/04 , G11C11/404 , G11C16/04 , G11C15/00
Abstract: A TCAM comprises a plurality of first search lines, a plurality of second search lines, a plurality of memory cell strings and one or more current sensing units. The memory cell strings comprise a plurality of memory cells. Each of the memory cells is coupled to one of the first search lines and one of the second search lines. The current sensing units, coupled to the memory cell strings. In a search operation, a determination that whether any of the data stored in the memory cell strings matches a data string to be searched is made according to whether the one or more current sensing units detect current from the memory cell strings, or according to the magnitude of the current flowing out from the memory cell strings detected by the one or more current sensing units.
-
公开(公告)号:US20220246218A1
公开(公告)日:2022-08-04
申请号:US17166484
申请日:2021-02-03
Applicant: MACRONIX International Co., Ltd.
Inventor: Feng-Min Lee , Po-Hao Tseng , Yu-Hsuan Lin , Ming-Hsiu Lee
IPC: G11C16/30 , H01L29/788 , G11C16/24 , G11C16/08 , G11C16/16 , H01L29/792 , H01L27/1157 , H01L27/11573 , H01L27/11524 , H01L27/11529 , G11C11/56 , H01L29/423
Abstract: A flash memory cell includes a rectifying device and a transistor. The rectifying device has an input end coupled to a bit line. The transistor has a charge storage structure. The transistor has a first end coupled to an output end of the rectifying device, the transistor has a second end coupled to a source line, and a control end of the transistor is coupled to a word line.
-
公开(公告)号:US20220237405A1
公开(公告)日:2022-07-28
申请号:US17344698
申请日:2021-06-10
Applicant: MACRONIX International Co., Ltd.
Inventor: Yun-Yuan Wang , Feng-Min Lee , Po-Hao Tseng , Ming-Hsiu Lee
Abstract: A data recognition apparatus and a recognition method are provided. The data recognition apparatus includes a data augmentation device, a feature extractor, and a comparator. The data augmentation device receives a plurality of target information and performs augmentation on each of the target information to generate a plurality of augmented target information. The feature extractor receives queried information and the augmented target information to extract features of the augmented target information and the queried information to respectively generate a plurality of augmented target feature values and a queried feature value. The comparator generates a recognition result according to the queried feature value and the augmented target feature values.
-
-
-
-
-
-
-
-
-