UNIVERSAL MEMORIES FOR IN-MEMORY COMPUTING

    公开(公告)号:US20250086443A1

    公开(公告)日:2025-03-13

    申请号:US18464718

    申请日:2023-09-11

    Abstract: A universal memory device includes an array of universal memory cells. Each universal memory cell includes a write transistor and a read transistor. The write transistor has a gate terminal configured to receive a gate voltage to turn on or off the write transistor, a first terminal configured to receive a write voltage, and a second terminal coupled to a gate terminal of the read transistor. The read transistor includes a charge trap layer at the gate terminal of the read transistor. The charge trap layer is configured to: be unalterable when the first write voltage is applied at the first terminal of the write transistor, and be alterable when the second write voltage is applied at the first terminal of the write transistor to change a threshold voltage of the read transistor. The second write voltage is greater than the first write voltage.

    Hybrid type content addressable memory for implementing in-memory-search and operation method thereof

    公开(公告)号:US12142319B2

    公开(公告)日:2024-11-12

    申请号:US17846304

    申请日:2022-06-22

    Abstract: A hybrid type content addressable memory for implementing in-memory-search and an operation method thereof are provided. The CAM includes a plurality of CAM strings and at least one sense amplifier circuit. Each of the CAM strings includes a plurality of CAM cells. The CAM cells store a plurality of existing data. The sense amplifier circuit is connected to the CAM strings. A plurality of search data are inputted to the CAM strings. A plurality of cell matching results obtained from the CAM cells in each of the CAM strings are integrated via an AND operation to obtain a string matching result. The string matching results obtained from the CAM strings are integrated via an OR operation.

    Memory device for in-memory computing, computing method and computing cell thereof

    公开(公告)号:US12057162B2

    公开(公告)日:2024-08-06

    申请号:US17929318

    申请日:2022-09-02

    CPC classification number: G11C13/0002 H03K19/20

    Abstract: An in-memory-computing method for a memory device includes: storing weight values in cascaded computing cells each including first and second computing memory cells, wherein the first computing memory cells are cascaded in series into a first computing memory cell string and the second computing memory cells are cascaded in series into a second computing memory cell string: receiving input values by the first and the second computing memory cell strings; performing a first logic operation on the input values and the weight values by the first computing memory cell string to generate a first logic operation result, and performing a second logic operation on the input values and the weight values by the second computing memory cell string to generate a second logic operation result: and performing a third logic operation on the first and the second logic operation results to generate an output logic operation result.

    Content-addressable memory and analog content-addressable memory device

    公开(公告)号:US11756620B2

    公开(公告)日:2023-09-12

    申请号:US17463607

    申请日:2021-09-01

    CPC classification number: G11C15/046

    Abstract: A memory cell for an analog content-addressable memory is provided. The memory cell includes an N-type transistor, a P-type transistor, and a current control circuit. The gate of the N-type transistor is configured to receive a first input signal. The gate of the P-type transistor is configured to receive a second input signal. The current control circuit is coupled to at least one of the N-type transistor and the P-type transistor. The current control circuit is configured to generate at least one passing current. When the input voltages of the first input signal and the second input signal are within a matching range, the N-type transistor and the P-type transistor are turned on, and the passing current is substantially a fixed current value. The matching range is related to the threshold voltages of the N-type transistor and the P-type transistor, and the fixed current value.

    Ternary content addressable memory and decision generation method for the same

    公开(公告)号:US11587617B2

    公开(公告)日:2023-02-21

    申请号:US17333046

    申请日:2021-05-28

    Abstract: A TCAM comprises a plurality of first search lines, a plurality of second search lines, a plurality of memory cell strings and one or more current sensing units. The memory cell strings comprise a plurality of memory cells. Each of the memory cells is coupled to one of the first search lines and one of the second search lines. The current sensing units, coupled to the memory cell strings. In a search operation, a determination that whether any of the data stored in the memory cell strings matches a data string to be searched is made according to whether the one or more current sensing units detect current from the memory cell strings, or according to the magnitude of the current flowing out from the memory cell strings detected by the one or more current sensing units.

    DATA RECOGNITION APPARATUS AND RECOGNITION METHOD THEREOF

    公开(公告)号:US20220237405A1

    公开(公告)日:2022-07-28

    申请号:US17344698

    申请日:2021-06-10

    Abstract: A data recognition apparatus and a recognition method are provided. The data recognition apparatus includes a data augmentation device, a feature extractor, and a comparator. The data augmentation device receives a plurality of target information and performs augmentation on each of the target information to generate a plurality of augmented target information. The feature extractor receives queried information and the augmented target information to extract features of the augmented target information and the queried information to respectively generate a plurality of augmented target feature values and a queried feature value. The comparator generates a recognition result according to the queried feature value and the augmented target feature values.

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