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公开(公告)号：US20240118971A1
公开(公告)日：2024-04-11
申请号：US18483091
申请日：2023-10-09
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , David Scott Ebsen , Akira Goda , Jonathan S. Parry , Vivek Shivhare , Suresh Rajgopal
CPC classification number: G06F11/1076 , G06F3/0619 , G06F3/0656 , G06F3/0659 , G06F3/0683
Abstract: Methods, systems, and apparatuses include allocating a temporary parity buffer to a parity group. A write command is received that includes user data and is directed to a portion of memory included in a zone which is included in the parity group. A memory identifier is determined for the portion of memory. Parity group data is received from the temporary parity buffer using the memory identifier. Updated parity group data is determined using the parity group data and the user data. The updated parity group data is sent to the temporary parity buffer.
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公开(公告)号：US20240087651A1
公开(公告)日：2024-03-14
申请号：US17941831
申请日：2022-09-09
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Huai-Yuan Tseng , Akira Goda , Dung V. Nguyen , Giovanni Maria Paolucci , James Fitzpatrick , Eric N. Lee , Dave Scott Ebsen , Tomoharu Tanaka
CPC classification number: G11C16/102 , G11C16/26 , G11C16/32
Abstract: Exemplary methods, apparatuses, and systems include an adaptive pre-read manager for controlling pre-reads of the memory device. The adaptive pre-read manager receives a first set of data bits for programming to memory. The adaptive pre-read manager performing a first pass of programming including a first subset of data bits from the set of data bits. The adaptive pre-read manager compares a set of threshold operating differences to a set of differences between multiple operating conditions during the first pass of programming and current operating conditions. The adaptive pre-read manager performs an internal pre-read of the programmed first subset of data bits. The adaptive pre-read manager performs a second pass of programming using the internal pre-read and a second subset of data bits from the first set of data bits.
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公开(公告)号：US11922029B2
公开(公告)日：2024-03-05
申请号：US17863000
申请日：2022-07-12
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Kishore Kumar Muchherla , Jonathan S. Parry , Nicola Ciocchini , Animesh Roy Chowdhury , Akira Goda , Jung Sheng Hoei , Niccolo' Righetti , Ugo Russo
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0653 , G06F3/0679
Abstract: A system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. The processing device is to receive a first read command at a first time. The first read command is with respect to a set of memory cells of the memory device. The processing device is further to receive a second read command at a second time. The second read command is with respect to the set of memory cells of the memory device. The processing device is further to increment a read counter for the memory device by a value reflecting a difference between the first time and the second time. The processing device is further to determine that a value of the read counter satisfies a threshold criterion. The processing device is further to perform a data integrity scan with respect to the set of memory cells.
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公开(公告)号：US11908948B2
公开(公告)日：2024-02-20
申请号：US17821414
申请日：2022-08-22
Applicant: Micron Technology, Inc.
Inventor： Kamal M. Karda , Guangyu Huang , Haitao Liu , Akira Goda
IPC: H01L29/786 , H01L29/66 , H10B41/41 , H10B43/40
CPC classification number: H01L29/7869 , H01L29/66969 , H10B41/41 , H10B43/40
Abstract: A transistor comprises a lower contact structure, a channel structure, a dielectric fill structure, and an upper contact structure. The lower contact structure comprises a first oxide semiconductive material. The channel structure contacts the lower contact structure and comprises a second oxide semiconductive material having a smaller atomic concentration of one or more metals than the first oxide semiconductive material. The dielectric fill structure contacts an inner side surface of the channel structure and has a recessed upper surface relative to the channel structure. The upper contact structure comprises a third oxide semiconductive material having a greater atomic concentration of the one or more metals than the channel structure. The upper contact structure comprises a first portion contacting the upper surface of the dielectric fill structure and the inner side surface of the channel structure, and a second portion contacting the upper surface of the channel structure.
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公开(公告)号：US20240045616A1
公开(公告)日：2024-02-08
申请号：US17882355
申请日：2022-08-05
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Lakshmi Kalpana Vakati , Dave Scott Ebsen , Peter Feeley , Sanjay Subbarao , Vivek Shivhare , Jiangli Zhu , Fangfang Zhu , Akira Goda
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0656 , G06F3/064 , G06F3/0619 , G06F3/0683
Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first and second block and a first and second user data portion are directed to the first and second block. Temporary parity data is generated using the first and second user data portions. The temporary parity data and the first and second user data portions are stored in a buffer. Portions of the first and second block are programmed with two programming passes. The first and second user data portions in the buffer are invalidated in response to a completion of the second programming pass of the portions of the first and second blocks. The temporary parity data is maintained in the buffer until a second programming pass of the first and second block.
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Patent Agency Ranking
公开(公告)号：US20240028252A1
公开(公告)日：2024-01-25
申请号：US17872426
申请日：2022-07-25
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Dung V. Nguyen , Dave Scott Ebsen , Tomoharu Tanaka , James Fitzpatrick , Huai-Yuan Tseng , Akira Goda , Eric N. Lee
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/064 , G06F3/0604 , G06F3/0679
Abstract: Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.
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公开(公告)号：US11861233B2
公开(公告)日：2024-01-02
申请号：US17691467
申请日：2022-03-10
Applicant: Micron Technology, Inc.
Inventor： Jeffrey S. McNeil , Kishore Kumar Muchherla , Sivagnanam Parthasarathy , Patrick R. Khayat , Sundararajan Sankaranarayanan , Jeremy Binfet , Akira Goda
CPC classification number: G06F3/0659 , G06F3/0619 , G06F3/0673 , G11C16/26 , G11C16/0483
Abstract: A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving data to be stored on the memory device, storing a first copy of the data in a first set of memory cells of the memory device, and storing a second copy of the data in a second set of memory cells of the memory device. The operations can also include reading the first copy of the data and determining whether a threshold voltage of a cell in the first set of memory cells is within an overlapping range of voltage distributions, and reading the second copy of the data and determining whether the threshold voltage of a cell in the second set of memory cells is within an overlapping range of voltage distributions. They can also include using the second copy of the data.
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公开(公告)号：US20230393756A1
公开(公告)日：2023-12-07
申请号：US17863000
申请日：2022-07-12
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Kishore Kumar Muchherla , Jonathan S. Parry , Nicola Ciocchini , Animesh Roy Chowdhury , Akira Goda , Jung Sheng Hoei , Niccolo' Righetti , Ugo Russo
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0679 , G06F3/0653
Abstract: A system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. The processing device is to receive a first read command at a first time. The first read command is with respect to a set of memory cells of the memory device. The processing device is further to receive a second read command at a second time. The second read command is with respect to the set of memory cells of the memory device. The processing device is further to increment a read counter for the memory device by a value reflecting a difference between the first time and the second time. The processing device is further to determine that a value of the read counter satisfies a threshold criterion. The processing device is further to perform a data integrity scan with respect to the set of memory cells.
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公开(公告)号：US11789629B2
公开(公告)日：2023-10-17
申请号：US17846462
申请日：2022-06-22
Applicant: Micron Technology, Inc.
Inventor： Kishore K. Muchherla , Niccolo' Righetti , Jeffrey S. McNeil, Jr. , Akira Goda , Todd A. Marquart , Mark A. Helm , Gil Golov , Jeremy Binfet , Carmine Miccoli , Giuseppina Puzzilli
IPC: G06F3/06
CPC classification number: G06F3/0644 , G06F3/0616 , G06F3/0619 , G06F3/0653 , G06F3/0656 , G06F3/0673
Abstract: A system includes a processing device and trigger circuitry to signal the processing device responsive, at least in part, based on a determination that a trigger event has occurred. The system can further include a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion having a first endurance characteristic and a first reliability characteristic associated therewith. The memory device can further include a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can have a second endurance characteristic and a second reliability characteristic associated therewith. The processing device can perform operations including writing received data sequentially to the cyclic buffer partition portion and writing, based at least in part on the determination that the trigger event has occurred, data from the cyclic buffer partition portion to the snapshot partition portion.
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公开(公告)号：US11775208B2
公开(公告)日：2023-10-03
申请号：US17829861
申请日：2022-06-01
Applicant: Micron Technology, Inc.
Inventor： Kishore K. Muchherla , Niccolo′ Righetti , Jeffrey S. McNeil, Jr. , Akira Goda , Todd A. Marquart , Mark A. Helm , Gil Golov , Jeremy Binfet , Carmine Miccoli , Giuseppina Puzzilli
CPC classification number: G06F3/0656 , G06F1/263 , G06F3/0613 , G06F3/0619 , G06F3/0644 , G06F3/0653 , G06F3/0673
Abstract: A system includes a processing device and a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion and a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can further include a first sub-partition portion having a first programming characteristic and a second sub-partition portion having a second programming characteristic. The processing device can write received data sequentially to the cycle buffer partition portion and write, based at least in part on a determination that a trigger event has occurred, data from the cyclic buffer partition portion to the first sub-partition portion or the second sub-partition portion, or both.
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