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    Object oriented memory in solid state devices
    72.
    发明授权
    Object oriented memory in solid state devices 有权
    固态设备中面向对象的内存

    公开(公告)号：US09110832B2

    公开(公告)日：2015-08-18

    申请号：US14269397

    申请日：2014-05-05

    Applicant: Micron Technology, Inc.

    Inventor： Peter Feeley ,  Neal A. Galbo ,  James Cooke ,  Victor Y. Tsai ,  Robert N. Leibowitz ,  William H. Radke

    IPC: G06F11/16 ,  G06F11/10 ,  G06F11/20 ,  G06F12/02 ,  G11C29/52

    CPC classification number: G06F11/1068 ,  G06F11/2064 ,  G06F12/0246 ,  G11C29/52

    Abstract: The present disclosure includes methods, devices, and systems for object oriented memory in solid state devices. One embodiment of a method for object oriented memory in solid state devices includes accessing a defined set of data as a single object in an atomic operation manner, where the accessing is from a source other than a host. The embodiment also includes storing the defined set of data as the single object in a number of solid state memory blocks as formatted by a control component of a solid state device that includes the number of solid state memory blocks.

    Abstract translation: 本公开包括固态设备中用于面向对象的存储器的方法，设备和系统。 在固态设备中面向对象存储器的方法的一个实施例包括以原子操作方式访问定义的一组数据作为单个对象，其中访问来自除主机之外的源。 该实施例还包括将定义的一组数据作为单个对象存储在多个固态存储器块中，如由固态存储器块的数量的固态设备的控制部件格式化。

    MEMORY DEVICES AND CONFIGURATION METHODS FOR A MEMORY DEVICE
    74.
    发明申请
    MEMORY DEVICES AND CONFIGURATION METHODS FOR A MEMORY DEVICE 有权
    用于存储器件的存储器件和配置方法

    公开(公告)号：US20150033096A1

    公开(公告)日：2015-01-29

    申请号：US14513880

    申请日：2014-10-14

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： William H. Radke ,  Tommaso Vali ,  Michele Incarnati

    IPC: G06F12/06 ,  G06F12/02 ,  G06F3/06 ,  G06F11/10

    CPC classification number: G06F11/1048 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0629 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/1072 ,  G06F12/0207 ,  G06F12/0646 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/52

    Abstract: A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure a first block of memory cells in a first configuration comprising one or more groups of overhead data memory cells, and to configure a second block of memory cells in a second configuration comprising one or more groups of user data memory cells and at least one group of overhead data memory cells. The first configuration is different than the second configuration. At least one group of overhead data memory cells of the second block of memory cells comprises a different storage capacity than at least one group of overhead data memory cells of the first block of memory cells.

    Abstract translation: 存储器设备具有多个可单独擦除的存储器单元块，以及控制器，被配置为配置包括一组或多组开销数据存储单元的第一配置中的第一存储单元块，并且配置存储器单元的第二块 包括一组或多组用户数据存储器单元和至少一组开销数据存储器单元的第二配置。 第一配置与第二配置不同。 存储器单元的第二块的至少一组开销数据存储单元包括与第一存储单元块的至少一组开销数据存储单元不同的存储容量。

    ERROR RECOVERY STORAGE ALONG A MEMORY STRING
    75.
    发明申请
    ERROR RECOVERY STORAGE ALONG A MEMORY STRING 有权
    存储器字符串中的错误恢复存储

    公开(公告)号：US20140325317A1

    公开(公告)日：2014-10-30

    申请号：US14263825

    申请日：2014-04-28

    Applicant: Micron Technology, Inc.

    Inventor： William H. Radke

    IPC: G06F11/10

    CPC classification number: G06F11/1008 ,  G06F11/1072 ,  H03M13/256 ,  H03M13/2909

    Abstract: Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. By using separate dimensions, the likelihood that a defect affects both error recovery techniques is lessened, thereby increasing the probability that error recovery can be performed successfully. In one example, block error correction codes are used for data stored along rows, and this data is stored in one level of multiple-level cells of the array. Supplemental error correction codes are used for data stored along columns, such as along the cells of a string, and the supplemental error correction codes are stored in a different level than the error correction codes.

    Abstract translation: 设备和方法存储存储器阵列的不同维度的错误恢复数据。 例如，在一个维度中，使用块纠错码（ECC），并且在另一维度中，使用补码纠错码，例如卷积码。 通过使用单独的维度，缺陷影响两种错误恢复技术的可能性减弱，从而增加了可以成功执行错误恢复的概率。 在一个示例中，块错误校正码用于沿着行存储的数据，并且该数据被存储在阵列的多级单元中。 补充纠错码用于沿列存储的数据，例如沿着字符串的单元格，并且补充纠错码存储在与纠错码不同的电平上。

    DATA CONDITIONING TO IMPROVE FLASH MEMORY RELIABILITY
    76.
    发明申请
    DATA CONDITIONING TO IMPROVE FLASH MEMORY RELIABILITY 有权
    数据调节提高闪存可靠性

    公开(公告)号：US20140298088A1

    公开(公告)日：2014-10-02

    申请号：US14308040

    申请日：2014-06-18

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： William H. Radke ,  Vishal Sarin ,  Jung-Sheng Hoei

    IPC: G06F11/10 ,  G11C29/52

    CPC classification number: G06F11/1072 ,  G06F12/0246 ,  G06F2212/7205 ,  G06F2212/7208 ,  G11C11/5628 ,  G11C29/52 ,  G11C2211/5641

    Abstract: Methods for managing data stored in a memory device facilitate managing utilization of memory of different densities. The methods include reading first data from a first number of pages or blocks of memory cells having a first density, performing a data handling operation on the read first data to generate second data, and writing the second data to a second number of pages or blocks of memory cells having a second density, wherein the second density is different than the first density, and wherein the second number is different than the first number.

    Abstract translation: 用于管理存储在存储设备中的数据的方法便于管理不同密度的存储器的利用。 所述方法包括从具有第一密度的第一页数或块的存储单元读取第一数据，对读取的第一数据执行数据处理操作以产生第二数据，以及将第二数据写入第二数量的页或块 的具有第二密度的存储单元，其中所述第二密度不同于所述第一密度，并且其中所述第二数量不同于所述第一密度。

    DATA MODULATION FOR GROUPS OF MEMORY CELLS
    77.
    发明申请
    DATA MODULATION FOR GROUPS OF MEMORY CELLS 有权
    记忆细胞群的数据调制

    公开(公告)号：US20140286094A1

    公开(公告)日：2014-09-25

    申请号：US14224925

    申请日：2014-03-25

    Applicant: Micron Technology, Inc.

    Inventor： Zhenlei Shen ,  William H. Radke

    IPC: G11C16/10

    CPC classification number: G11C16/10 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/34

    Abstract: Methods, devices, and systems for data modulation for groups of memory cells. Data modulation for groups of memory cells can include modulating N units of data to a combination of programmed states. Each memory cell of a group of G number of memory cells can be programmed to one of M number of programmed states, where M is greater than a minimum number of programmed states needed to store N/G units of data in one memory cell, and where the programmed state of each memory cell of the group is one of the combination of programmed states.

    Abstract translation: 用于存储器单元组的数据调制的方法，设备和系统。 存储器单元组的数据调制可以包括将N个数据单元调制为编程状态的组合。 一组G个存储器单元的每个存储器单元可以被编程为M个编程状态中的一个，其中M大于在一个存储器单元中存储N / G个数据单元所需的编程状态的最小数量，以及 其中组的每个存储器单元的编程状态是编程状态的组合之一。

    Methods, devices, and systems for dealing with threshold voltage change in memory devices
    78.
    发明授权
    Methods, devices, and systems for dealing with threshold voltage change in memory devices 有权
    用于处理存储器件中阈值电压变化的方法，器件和系统

    公开(公告)号：US08830762B2

    公开(公告)日：2014-09-09

    申请号：US14056713

    申请日：2013-10-17

    Applicant: Micron Technology, Inc.

    Inventor： Zhenlei Shen ,  William H. Radke ,  Peter Feeley

    IPC: G11C16/06

    CPC classification number: G11C16/34 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3495

    Abstract: The present disclosure includes methods, devices, and systems for dealing with threshold voltage change in memory devices. A number of embodiments include an array of memory cells and control circuitry having sense circuitry coupled to the array. The control circuitry is configured to determine changes in threshold voltages (Vts) associated with the memory cells without using a reference cell, and adjust the sense circuitry based on the determined changes and without using a reference cell.

    Abstract translation: 本公开包括用于处理存储器件中的阈值电压变化的方法，装置和系统。 多个实施例包括具有耦合到阵列的感测电路的存储器单元阵列和控制电路。 控制电路被配置为确定与存储器单元相关联的阈值电压（Vts）的变化而不使用参考单元，并且基于所确定的变化并且不使用参考单元来调整感测电路。

    Methods, devices, and systems for adjusting sensing voltages in devices
    79.
    发明授权
    Methods, devices, and systems for adjusting sensing voltages in devices 有权
    用于调整设备中感应电压的方法，设备和系统

    公开(公告)号：US08797803B2

    公开(公告)日：2014-08-05

    申请号：US13746689

    申请日：2013-01-22

    Applicant: Micron Technology, Inc.

    Inventor： William H. Radke ,  Zhenlei Shen ,  Peter Feeley

    IPC: G11C16/26

    CPC classification number: G11C16/28 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26

    Abstract: The present disclosure includes methods, devices, and systems for adjusting sensing voltages in devices. One or more embodiments include memory cells, and a controller configured to perform a sense operation on the memory cells using a sensing voltage to determine a quantity of the memory cells having a threshold voltage (Vt) greater than the sensing voltage and adjust a sensing voltage used to determine a state of the memory cells based, at least partially, on the determined quantity of memory cells.

    Abstract translation: 本公开包括用于调整设备中的感测电压的方法，设备和系统。 一个或多个实施例包括存储器单元和被配置为使用感测电压对存储器单元执行感测操作的控制器，以确定具有大于感测电压的阈值电压（Vt）的存储器单元的数量并且调整感测电压 用于至少部分地基于所确定的存储器单元的数量来确定存储器单元的状态。

    PACKET DECONSTRUCTION/RECONSTRUCTION AND LINK-CONTROL
    80.
    发明申请
    PACKET DECONSTRUCTION/RECONSTRUCTION AND LINK-CONTROL 有权
    分组分解/重构和链接控制

    公开(公告)号：US20140185620A1

    公开(公告)日：2014-07-03

    申请号：US14108599

    申请日：2013-12-17

    Applicant: Micron Technology, Inc.

    Inventor： William H. Radke ,  Victor Y. Tsai ,  Peter Feeley ,  Neal A. Galbo ,  Robert N. Leibowitz

    IPC: H04L12/801

    CPC classification number: H04L47/34 ,  H04L1/1867 ,  H04L47/27 ,  H04L69/324

    Abstract: The present disclosure includes methods, devices, and systems for packet processing. One method embodiment for packet flow control includes deconstructing a transport layer packet into a number of link-control layer packets, wherein each of the link-control layer packets has an associated sequence number, communicating the number of link-control layer packets via a common physical connection for a plurality of peripheral devices, and limiting a number of outstanding link-control layer packets during the communication.

    Abstract translation: 本公开包括用于分组处理的方法，设备和系统。 用于分组流控制的一个方法实施例包括将传输层分组解构成多个链路控制层分组，其中链路控制层分组中的每一个具有相关联的序列号，经由共同的通信来传送链路控制层分组的数量 用于多个外围设备的物理连接，并且在通信期间限制多个未完成的链路控制层分组。

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