公开(公告)号：US20230058855A1

公开(公告)日：2023-02-23

申请号：US17409431

申请日：2021-08-23

Applicant: MACRONIX International Co., Ltd.

Inventor： Li-Yen Liang ,  Teng-Hao Yeh

IPC: H01L27/1157 ,  H01L23/522 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11565

Abstract: A 3D flash memory device such as a 3D AND flash memory device is provided. The 3D flash memory device includes a substrate, a conductive layer, a 3D flash memory array, and through-array vias (TAVs). The substrate includes a memory cell region and a passive device region. The conductive layer is formed on the substrate, and the conductive layer includes: a first circuit disposed at the memory cell region and a second circuit of a passive device disposed at the passive device region. The 3D flash memory array is formed on the first circuit of the memory cell region. The TAVs are respectively formed on the second circuit of the passive device disposed at the passive device region and connected to at least one end of the second circuit.

公开(公告)号：US11551072B2

公开(公告)日：2023-01-10

申请号：US16872404

申请日：2020-05-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Cheng-Lin Sung ,  Teng-Hao Yeh

IPC: G06N3/063 ,  G11C11/54 ,  G06N3/04 ,  G11C16/26 ,  G11C16/24

Abstract: A spiking neural networks circuit and an operation method thereof are provided. The spiking neural networks circuit includes a bit-line input synapse array and a neuron circuit. The bit-line input synapse array includes a plurality of page buffers, a plurality of bit line transistors, a plurality of bit lines, a plurality of memory cells, one word line, a plurality of source lines and a plurality of source line transistors. The page buffers provides a plurality of data signals. Each of the bit line transistors is electrically connected to one of the page buffers. Each of the bit lines receives one of the data signals. The source line transistors are connected together. The neuron circuit is for outputting a feedback pulse.

公开(公告)号：US11101287B2

公开(公告)日：2021-08-24

申请号：US16693507

申请日：2019-11-25

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

IPC: H01L27/11582 ,  H01L27/11565

Abstract: A three-dimensional memory device includes a plurality of conductive layers and insulating layers alternately formed to define a multi-layer stacked structure. The multi-layer stacked structure includes a stair region and an non-stair region, the stair region includes a plurality of steps, each step includes an immediately-adjacent pair of the conductive layers and insulating layers. A plurality of memory structures are located in the non-stair region, and each memory structure passes through the conductive layers and the insulating layers. A fishbone dielectric structure includes a main bone and a plurality of side bones extending from the main bone in the stair region, wherein the main bone crosses the memory structures in the non-stair region.

公开(公告)号：US10930669B2

公开(公告)日：2021-02-23

申请号：US16273301

申请日：2019-02-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh ,  Yu-Wei Jiang

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L29/792 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L21/28

Abstract: A three-dimensional memory device includes a substrate, conductive layers and insulating layers, a storage layer, a first channel, a second channel and a first conductive plug. The conductive layers and insulating layers are alternately stacked over the substrate to form a multi-layer stacked structure. The storage layer penetrates through the multi-layer stacked structure, and has a first string portion and a second string portion that are spaced from each other. The first channel is located on a lateral side of the first string portion. The second channel is located on a lateral side of the second string portion. The first channel and the second channel have an upper channel portion and a lower channel portion. The first conductive plug is interconnected between the upper channel portion and the lower channel portion.

公开(公告)号：US10790028B1

公开(公告)日：2020-09-29

申请号：US16576652

申请日：2019-09-19

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Lee-Yin Lin

IPC: G11C16/24 ,  G11C5/02 ,  H01L27/11582 ,  H01L27/11556 ,  G11C5/06

Abstract: An AND type flash memory includes a memory cell array, a plurality of page buffers and a plurality of voltage shifting circuits. The memory cell array is coupled to a plurality of bits lines and source lines. The page buffers are respectively coupled to the bit lines through a plurality of switches, and respectively provides a plurality of control signals. The control signals are transited between a first voltage and a reference voltage. The voltage shifting circuits respectively receive the control signals, generates a plurality of driving signals by shifting voltage values of the control signals, and provides the driving signals to the bit lines. Wherein, the driving signals are transited between a second voltage and the reference voltage, the second voltage is larger than the first voltage.

公开(公告)号：US10388720B2

公开(公告)日：2019-08-20

申请号：US15279203

申请日：2016-09-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue ,  Teng-Hao Yeh

IPC: H01L27/02 ,  H01L27/06 ,  H01L49/02 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: An integrated circuit includes a 3D NAND memory array with a stack of conductive strips and a capacitor with a stack of capacitor terminal strips. Multiple conductive strips in the stack of conductive strips, and multiple capacitor terminal strips of the stack of capacitor terminal strips, share a same plurality of plane positions relative to the substrate. Different plane positions in the same plurality of plane positions characterize different capacitor terminal strips in the stack of capacitor terminal strips and different conductive strips in the stack of conductive strips, and a same plane position characterizing both a conductive strip in the stack of conductive strips and a capacitor terminal strip in the stack of capacitor terminal strips indicates that the conductive strip and the capacitor terminal strip have a same vertical position relative to each other.

公开(公告)号：US09721668B2

公开(公告)日：2017-08-01

申请号：US14820209

申请日：2015-08-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao Yeh ,  Kuo-Pin Chang

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/08 ,  H01L27/24

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/08 ,  H01L27/24

Abstract: A memory device has a divided reference line structure which supports sub-block erase in NAND memory including a plurality of blocks. Each block in the plurality of blocks is coupled to a set of Y reference lines, where Y is two or more. Each block in the plurality of blocks includes a single reference select line (RSL), which is operable to connect each sub-block in the block to a corresponding reference line in the set of Y reference lines. A control circuit can be included on the device which is configured for an erase operation to erase a selected sub-block in a selected block.

公开(公告)号：US09716137B1

公开(公告)日：2017-07-25

申请号：US15285808

申请日：2016-10-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

IPC: H01L23/52 ,  H01L49/02 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L28/90 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L28/60

Abstract: An integrated circuit includes 3D memory blocks and 3D capacitor blocks. The 3D capacitor comprises a plurality of stacks of conductive strips alternating with insulating strips, and a first terminal connected to conductive strips in consecutive levels in one or more stacks, whereby the conductive strips act as a first plate of the 3D capacitor. A second terminal is insulated from the first terminal, either connected to conductive strips in consecutive levels in another or other stacks, or connected to a plurality of pillars. No intervening conductive strip is disposed between the conducive strips in consecutive levels.

公开(公告)号：US09627498B2

公开(公告)日：2017-04-18

申请号：US14717177

申请日：2015-05-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Jia-Rong Chiou ,  Yu-Wei Jiang ,  Teng-Hao Yeh

IPC: H01L21/768 ,  H01L21/70 ,  H01L29/45 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66 ,  H01L29/786 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11548 ,  H01L27/11575

CPC classification number: H01L29/458 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76859 ,  H01L23/485 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/6675 ,  H01L29/78672

Abstract: A method is described for forming a circuit that comprises forming a layer of semiconductor material on the substrate and an interlayer conductor contacting the layer. The layer can be a thin film layer. An opening is etched in an interlayer insulator over a layer of semiconductor material, to expose a landing area on the layer of semiconductor material. The semiconductor material exposed by the opening is thickened by adding some of the semiconductor material within the opening. The process for adding the semiconductor material can include a blanket deposition, or a selective growth only within the landing area. A reaction precursor, such as a silicide precursor is deposited on the landing area in the opening. A reaction of the precursor with the semiconductor material in the opening is induced. An interlayer conductor is formed within the opening.

公开(公告)号：US20160329344A1

公开(公告)日：2016-11-10

申请号：US14704706

申请日：2015-05-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao Yeh ,  Chih-Wei Hu ,  Lee-Yin Lin

IPC: H01L27/115 ,  G11C16/14 ,  G11C16/26 ,  G11C16/24

CPC classification number: H01L27/11582 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C5/063 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: The area consumed by switching transistors for a 3D NAND memory array can be reduced with 3D voltage switching transistors with reduced aggregate area in comparison with 2D voltage switching transistors such as transistors in the substrate. The integrated circuit comprises a 3D NAND array of memory transistors; a plurality of bit lines, with different ones of the plurality of bit lines electrically coupled to different parts of the 3D NAND array; and a plurality of transistor pairs with a stack of semiconductor layers. Different layers in the stack of semiconductor layers include different transistor pairs of the plurality of transistor pairs. Each of the plurality of transistor pairs includes first and second transistors with first, second, and third source/drain terminals. The first transistor includes the first and the third source/drain terminals, and the second transistor includes the second and the third source/drain terminals. The first source/drain terminal is electrically coupled to an erase voltage line. The second source/drain terminal is electrically coupled to a corresponding one of a plurality of program/read voltage lines. The third source/drain terminal is electrically coupled to a corresponding one of the plurality of bit lines.

Abstract translation: 与2D基板中的晶体管等2D电压开关晶体管相比，3D NAND存储器阵列的开关晶体管消耗的面积可以减小，具有减小的聚集面积的3D电压开关晶体管。 集成电路包括存储晶体管的3D NAND阵列; 多个位线，其中多个位线中的不同的位线电耦合到3D NAND阵列的不同部分; 以及具有堆叠半导体层的多个晶体管对。 半导体层堆叠中的不同层包括多个晶体管对的不同晶体管对。 多个晶体管对中的每一个包括具有第一，第二和第三源极/漏极端子的第一和第二晶体管。 第一晶体管包括第一和第三源极/漏极端子，第二晶体管包括第二和第三源极/漏极端子。 第一源极/漏极端子电耦合到擦除电压线。 第二源极/漏极端子电耦合到多个编程/读取电压线中的对应的一个。 第三源极/漏极端子电耦合到多个位线中的对应的一个位线。