公开(公告)号：US07570144B2

公开(公告)日：2009-08-04

申请号：US11750341

申请日：2007-05-18

申请人： Chee Chong Lim ,  Kok Wai Chew ,  Kiat Seng Yeo ,  Suh Fei Lim ,  Manh Anh Do ,  Lap Chan

发明人： Chee Chong Lim ,  Kok Wai Chew ,  Kiat Seng Yeo ,  Suh Fei Lim ,  Manh Anh Do ,  Lap Chan

IPC分类号： H01F5/00

CPC分类号： H01F17/0006 ,  H01F17/0013 ,  H01F19/08 ,  H01F27/2804 ,  H01F41/041 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10T29/4902 ,  H01L2924/00

摘要： An integrated transformer structure includes a first coil element associated with a transverse axis, the first coil element having at least one turn. The first coil element includes a first portion provided on a first lateral level, and a second portion provided on a second lateral level. The first and second lateral levels being mutually spaced apart along said transverse axis. The first and second portions being displaced laterally from said axis by different respective distances. At least one crossover portion of the first coil element, in which the first coil element being configured to provide a conducting path through at least a portion of the first portion of the first coil element to the crossover portion, through the crossover portion and subsequently through at least a portion of the second portion of the first coil element, in which any change of flow direction along said path is less than 90° in a lateral direction.

摘要翻译： 集成变压器结构包括与横向轴线相关联的第一线圈元件，第一线圈元件具有至少一匝。 第一线圈元件包括设置在第一横向水平面上的第一部分和设置在第二横向水平面上的第二部分。 第一和第二横向水平面沿着所述横向轴线相互间隔开。 第一和第二部分从所述轴线横向移位不同的相应距离。 所述第一线圈元件的至少一个交叉部分，其中所述第一线圈元件被配置为提供通过所述交叉部分穿过所述交叉部分的所述第一线圈元件的所述第一部分的至少一部分的导电路径，并且随后通过 第一线圈元件的第二部分的至少一部分，其中沿着所述路径的流动方向的任何变化在横向方向上小于90°。

公开(公告)号：US07112866B2

公开(公告)日：2006-09-26

申请号：US10796893

申请日：2004-03-09

申请人： Lap Chan ,  Cher Liang Cha ,  Kheng Chok Tee

发明人： Lap Chan ,  Cher Liang Cha ,  Kheng Chok Tee

IPC分类号： H01L29/00 ,  H01L23/48 ,  H01L21/331 ,  H01L21/4765

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention provides a new multilevel interconnect structure of air gaps in a layer of IMD. A first layer of dielectric is provided over a surface; the surface contains metal points of contact. Trenches are provided in this first layer of dielectric. The trenches are filled with a first layer of nitride or disposable solid and polished. A second layer of dielectric is deposited over the first layer of dielectric. Trenches are formed in the second layer of dielectric, a second layer of nitride or disposable solid is deposited over the second layer of dielectric. The layer of nitride or disposable solid is polished. A thin layer of oxide is deposited over the surface of the second layer of dielectric. The thin layer of oxide is masked and etched thereby creating openings in this thin layer of oxide, these openings align with the points of intersect of the trenches in the first layer of dielectric and in the second layer of dielectric. The nitride or removable solid is removed from the trenches. The openings in the thin layer of oxide are closed off leaving a network of trenches that are filled with air in the two layers of dielectric that now function as the Inter Level Dielectric.

摘要翻译： 本发明提供了在IMD层中的空气间隙的新的多层互连结构。 在表面上提供第一层电介质; 表面含有金属接触点。 在第一层电介质中设置沟槽。 沟槽填充有第一层氮化物或一次性固体并抛光。 第二层介质沉积在第一层电介质上。 沟槽形成在第二层电介质中，第二层氮化物或一次性固体沉积在第二层电介质上。 抛光氮化物或一次性固体层。 在第二电介质层的表面上沉积薄层的氧化物。 氧化物的薄层被掩蔽和蚀刻，从而在该薄层氧化物中形成开口，这些开口与第一介电层和第二介质层中的沟槽的交叉点对准。 氮化物或可移除的固体从沟槽中去除。 氧化物薄层中的开口被封闭，留下在两层电介质中充满空气的沟槽网络，现在这两层电介质用作Inter Level Dielectric。

公开(公告)号：US20060206852A1

公开(公告)日：2006-09-14

申请号：US11078820

申请日：2005-03-10

申请人： Andrew Khoh ,  Byong-Il Choi ,  Lap Chan ,  Ganesh Samudra ,  Yihong Wu

发明人： Andrew Khoh ,  Byong-Il Choi ,  Lap Chan ,  Ganesh Samudra ,  Yihong Wu

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A trial semiconductor photomask design having discontinuity points is provided, and each of the discontinuity points is treated as simulated light sources. Simulated light from each of the simulated light sources is focused, and a composite image intensity of the focused simulated light is calculated to verify the trial semiconductor photomask design. The trial semiconductor photomask design is sharpened. A photomask design specification is generated for use in fabricating such a photomask.

摘要翻译： 提供具有不连续点的试验半导体光掩模设计，将每个不连续点视为模拟光源。 聚焦每个模拟光源的模拟光，并计算聚焦模拟光的合成图像强度，以验证试验半导体光掩模设计。 试制半导体光掩模设计锐化。 生成光掩模设计规范用于制造这种光掩模。

公开(公告)号：US20060194397A1

公开(公告)日：2006-08-31

申请号：US11391506

申请日：2006-03-28

申请人： Lay Choo ,  James Lee ,  Lap Chan

发明人： Lay Choo ,  James Lee ,  Lap Chan

IPC分类号： H01L21/336

CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/76895 ,  H01L21/823481 ,  Y10S438/949

摘要： In accordance with the objects of this invention, a new method of fabricating a polysilicon gate transistor is achieved. An alternating aperture phase shift mask (AAPSM) is used to pattern polysilicon gates in a single exposure without a trim mask. A semiconductor substrate is provided. A gate dielectric layer is deposited. A polysilicon layer is deposited. The polysilicon layer, the gate dielectric layer and the semiconductor substrate are patterned to form trenches for planned shallow trench isolations (STI). A trench oxide layer is deposited filling the trenches. The trench oxide layer is polished down to the top surface of the polysilicon layer to complete the STI. A photoresist layer is deposited and patterned to form a feature mask for planned polysilicon gates. The patterning is by a single exposure using an AAPSM mask. Unwanted features in the photoresist pattern that are caused by phase conflicts overlie the STI. The polysilicon layer is etched to form the polysilicon gates.

公开(公告)号：US07060573B2

公开(公告)日：2006-06-13

申请号：US09759909

申请日：2001-01-16

申请人： Victor Seng Keong Lim ,  Feng Chen ,  Lap Chan ,  Wang Ling Goh

发明人： Victor Seng Keong Lim ,  Feng Chen ,  Lap Chan ,  Wang Ling Goh

IPC分类号： H01L21/336

CPC分类号： H01L21/76232

摘要： A new method of forming shallow trench isolations has been described. A silicon semiconductor substrate is provided. A silicon nitride layer is deposited overlying the substrate. A polysilicon layer is deposited overlying the silicon nitride layer. An oxidation mask is deposited overlying the polysilicon layer. The oxidation mask, polysilicon layer, silicon nitride layer, and the silicon semiconductor substrate are patterned to form trenches for planned shallow trench isolations. The silicon semiconductor substrate exposed within the trenches is oxidized to form an oxide liner layer within the trenches wherein the oxidation mask prevents oxidation of the polysilicon layer. Thereafter the oxidation mask is removed. A trench oxide layer is deposited overlying the liner oxide layer and filling the trenches. The trench oxide layer and the polysilicon layer are polished down stopping at the silicon nitride layer with a polishing selectivity of oxide to polysilicon to nitride of 4:100:1 wherein dishing is avoided to complete shallow trench isolations in the manufacture of an integrated circuit device.

公开(公告)号：US07037791B2

公开(公告)日：2006-05-02

申请号：US10135071

申请日：2002-04-30

申请人： Lay Cheng Choo ,  James Yong Meng Lee ,  Lap Chan

发明人： Lay Cheng Choo ,  James Yong Meng Lee ,  Lap Chan

IPC分类号： H01L21/336 ,  G03C5/00 ,  G03C5/16

CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/76895 ,  H01L21/823481 ,  Y10S438/949

摘要： In accordance with the objects of this invention, a new method of fabricating a polysilicon gate transistor is achieved. An alternating aperture phase shift mask (AAPSM) is used to pattern polysilicon gates in a single exposure without a trim mask. A semiconductor substrate is provided. A gate dielectric layer is deposited. A polysilicon layer is deposited. The polysilicon layer, the gate dielectric layer and the semiconductor substrate are patterned to form trenches for planned shallow trench isolations (STI). A trench oxide layer is deposited filling the trenches. The trench oxide layer is polished down to the top surface of the polysilicon layer to complete the STI. A photoresist layer is deposited and patterned to form a feature mask for planned polysilicon gates. The patterning is by a single exposure using an AAPSM mask. Unwanted features in the photoresist pattern that are caused by phase conflicts overlie the STI. The polysilicon layer is etched to form the polysilicon gates.

公开(公告)号：US20050074939A1

公开(公告)日：2005-04-07

申请号：US10676896

申请日：2003-10-01

申请人： Vincent Ho ,  Wee Choi ,  Lap Chan ,  Wai Chim ,  Vivian Ng ,  Cheng Heng ,  Lee Teo

发明人： Vincent Ho ,  Wee Choi ,  Lap Chan ,  Wai Chim ,  Vivian Ng ,  Cheng Heng ,  Lee Teo

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/423 ,  H01L29/788

CPC分类号： B82Y10/00 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/7881 ,  Y10S438/962

摘要： Devices with embedded silicon or germanium nanocrystals, fabricated using ion implantation, exhibit superior data-retention characteristics relative to conventional floating-gate devices. However, the prior art use of ion implantation for their manufacture introduces several problems. These have been overcome by initial use of rapid thermal oxidation to grow a high quality layer of thin tunnel oxide. Chemical vapor deposition is then used to deposit a germanium doped oxide layer. A capping oxide is then deposited following which the structure is rapid thermally annealed to synthesize the germanium nanocrystals.

摘要翻译： 使用离子注入制造的具有嵌入式硅或锗纳米晶体的器件相对于常规浮栅器件表现出优异的数据保持特性。 然而，现有技术中使用离子注入来制造这些问题。 通过初始使用快速热氧化来生长高质量的薄隧道氧化物层，已经克服了这些。 然后使用化学气相沉积来沉积掺锗的氧化物层。 然后沉积封端氧化物，然后将结构快速热退火以合成锗纳米晶体。

公开(公告)号：US06835631B1

公开(公告)日：2004-12-28

申请号：US10718193

申请日：2003-11-20

申请人： Zheng Jia Zhen ,  Sanford Chu ,  Ng Chit Hwei ,  Lap Chan ,  Purakh Raj Verma

发明人： Zheng Jia Zhen ,  Sanford Chu ,  Ng Chit Hwei ,  Lap Chan ,  Purakh Raj Verma

IPC分类号： H01L2120

CPC分类号： H01L28/10 ,  H01L23/5222 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A method of enhancing inductor performance comprising the following steps. A structure having a first oxide layer formed thereover is provided. A lower low-k dielectric layer is formed over the first oxide layer. A second oxide layer is formed over the lower low-k dielectric layer. The second oxide layer is patterned to form at least one hole there through exposing a portion of the lower low-k dielectric layer. Etching through the exposed portion of the lower low-k dielectric layer and into the lower low-k dielectric layer to from at least one respective air gap within the etched lower low-k dielectric layer. An upper low-k dielectric layer is formed over the patterned second oxide layer. At least one inductor is formed within the upper low-k dielectric layer and over the at least one air gap whereby the performance of the inductor is enhanced.

摘要翻译： 一种提高电感器性能的方法，包括以下步骤。 提供一种其上形成有第一氧化物层的结构。 在第一氧化物层上形成较低的低k电介质层。 在下部低k电介质层上形成第二氧化物层。 图案化第二氧化物层以通过暴露下部低k电介质层的一部分而在其中形成至少一个孔。 通过下部低k介电层的暴露部分蚀刻到下部低k电介质层中，从而蚀刻下蚀刻的低k介电层内的至少一个相应的气隙。 在图案化的第二氧化物层上形成上部低k电介质层。 至少一个电感器形成在上部低k电介质层内并在至少一个气隙上形成，从而提高了电感器的性能。

公开(公告)号：US06777774B2

公开(公告)日：2004-08-17

申请号：US10125244

申请日：2002-04-17

申请人： Sia Choon Beng ,  Yeo Kiat Seng ,  Sanford Chu ,  Lap Chan ,  Chew Kok-Wai

发明人： Sia Choon Beng ,  Yeo Kiat Seng ,  Sanford Chu ,  Lap Chan ,  Chew Kok-Wai

IPC分类号： H01L2900

CPC分类号： H01L28/10 ,  H01L23/552 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： A novel complimentary shielded inductor on a semiconductor is disclosed. A region of electrically floating high resistive material is deposited between the inductor and the semiconductor substrate. The high resistive shield is patterned with a number of gaps, such that a current induced in the shield by the inductor does not have a closed loop path. The high resistive floating shield compliments a grounded low resistive shield to achieve higher performance inductors. In this fashion, noise in the substrate is reduced. The novel complimentary shield does not significantly degrade the figures of merit of the inductor, such as, quality factor and resonance frequency. In one embodiment, the grounded shield is made of patterned N-well (or P-well) structures. In still another embodiment, the low resistive electrically grounded shield is made of patterned Silicide, which may be formed on portions of the substrate itself.

摘要翻译： 公开了一种半导体上的新型有用屏蔽电感器。 电浮动高电阻材料的区域沉积在电感器和半导体衬底之间。 高电阻屏蔽层被图案化为多个间隙，使得由电感器在屏蔽层中感应的电流不具有闭环路径。 高电阻浮动屏蔽补充了接地的低电阻屏蔽以实现更高性能的电感器。 以这种方式，衬底中的噪声降低。 新型互补屏蔽不会显着降低电感器的品质因数，如品质因数和谐振频率。 在一个实施例中，接地屏蔽由图案化的N阱（或P阱）结构制成。 在另一个实施例中，低电阻电接地屏蔽由图案化的硅化物制成，其可以形成在衬底本身的部分上。

公开(公告)号：US06566650B1

公开(公告)日：2003-05-20

申请号：US09664418

申请日：2000-09-18

申请人： Chang Chaun Hu ,  Kin Leong Pey ,  Yung Fu Chong ,  Chim Wai Kin ,  Pavel Neuzil ,  Lap Chan

发明人： Chang Chaun Hu ,  Kin Leong Pey ,  Yung Fu Chong ,  Chim Wai Kin ,  Pavel Neuzil ,  Lap Chan

IPC分类号： B01D5944

CPC分类号： G01Q60/58 ,  Y10S977/867 ,  Y10S977/875

摘要： One of the limitations to current usage of scanning thermal microscopes arises when one needs to obtain a thermal map of an electrically biased specimen. Current practice is for the conductive parts of the specimen to be passivated to prevent excessive current leakage between the tip and the conductive sample. The present invention eliminates the need for this by coating the probe's microtip with a layer of insulation that is also a good thermal conductor. Examples of both thermocouple and thermistor based probes are given along with processes for their manufacture.

摘要翻译： 当需要获得电偏置样本的热图时，会出现当前使用扫描热显微镜的局限性。 目前的做法是使样品的导电部件被钝化，以防止尖端和导电样品之间的过大的电流泄漏。 本发明通过用也是良好热导体的绝缘层涂覆探针的微尖头来消除对此的需要。 给出了热电偶和基于热敏电阻的探针的实例以及其制造方法。