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    Apparatuses and methods for memory operations having variable latencies
    73.
    发明授权
    Apparatuses and methods for memory operations having variable latencies 有权

    公开(公告)号：US09754648B2

    公开(公告)日：2017-09-05

    申请号：US13794471

    申请日：2013-03-11

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Graziano Mirichigni ,  Corrado Villa ,  Luca Porzio

    IPC: G11C7/10 ,  G11C7/22 ,  G06F13/16

    CPC classification number: G11C7/22 ,  G06F13/1689 ,  G11C7/1063

    Abstract: Apparatuses and methods for performing memory operations are described. In an example apparatus, a memory is configured to receive a memory instruction and perform a memory operation responsive to the memory instruction. The memory is further configured to provide an acknowledgement indicative of an end of the variable latency period wherein the acknowledgement includes information related to an acceptance of a memory instruction. Data associated with the memory instruction is exchanged with the memory following the acknowledgement. In an example method a read instruction and an address from which read data is to be read is received. A write operation is suspended responsive to the read instruction and an acknowledgement indicative of an end of the variable latency period is provided. Read data for the read instruction is provided and the write operation is continued to be suspended for a hold-off period following completion of the read operation.

    METHOD AND APPARATUS TO PERFORM CONCURRENT READ AND WRITE MEMORY OPERATIONS
    78.
    发明申请
    METHOD AND APPARATUS TO PERFORM CONCURRENT READ AND WRITE MEMORY OPERATIONS 有权
    执行同时读和写存储器操作的方法和装置

    公开(公告)号：US20150309868A1

    公开(公告)日：2015-10-29

    申请号：US14793475

    申请日：2015-07-07

    Applicant: Micron Technology, Inc.

    Inventor： Graziano Mirichigni

    IPC: G06F11/10 ,  G11C29/52

    CPC classification number: G06F11/1048 ,  G06F11/1016 ,  G06F11/1044 ,  G06F11/1072 ,  G06F11/1096 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C29/52 ,  G11C2211/5623 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19 ,  H03M13/23 ,  H03M13/2909 ,  H03M13/6561

    Abstract: Subject matter disclosed herein relates to read and write processes of a memory device. During a write process to a particular partition in a memory array, a response to a read request of contents of the particular partition may be delayed. In some embodiments, the contents of the particular partition may be indirectly read during the write process without delaying the response to the read request. The contents of the particular partition can be indirectly read by determining the contents of the particular partition based, at least in part, on an error correction code based, at least in part, on contents of memory partitions of the memory array.

    Abstract translation: 本文公开的主题涉及存储器件的读取和写入过程。 在对存储器阵列中的特定分区的写入处理期间，可能延迟对特定分区的内容的读取请求的响应。 在一些实施例中，特定分区的内容可以在写入过程期间间接读取，而不会延迟对读请求的响应。 至少部分地基于至少部分地基于存储器阵列的存储器分区的内容的纠错码来确定特定分区的内容来间接读取特定分区的内容。

    METHODS AND APPARATUSES FOR REQUESTING READY STATUS INFORMATION FROM A MEMORY
    79.
    发明申请
    METHODS AND APPARATUSES FOR REQUESTING READY STATUS INFORMATION FROM A MEMORY 有权
    从存储器中请求准备状态信息的方法和装置

    公开(公告)号：US20150100744A1

    公开(公告)日：2015-04-09

    申请号：US14506414

    申请日：2014-10-03

    Applicant: Micron Technology, Inc.

    Inventor： Graziano Mirichigni ,  Danilo Caraccio ,  Luca Porzio

    IPC: G06F12/02

    CPC classification number: G06F12/023 ,  G06F3/0659 ,  G06F12/0246 ,  G06F13/1642

    Abstract: Methods and apparatuses are disclosed for requesting ready status information from a memory. One example apparatus includes a memory and a host coupled to the memory. The host is configured to provide a plurality of memory access requests to the memory, to request ready status information regarding whether the memory is ready to execute a memory access request of the plurality of memory access requests, and to request execution of the memory access request responsive to the ready status information.

    Abstract translation: 公开了用于从存储器请求就绪状态信息的方法和装置。 一个示例性设备包括存储器和耦合到存储器的主机。 主机被配置为向存储器提供多个存储器访问请求，以请求关于存储器是否准备好执行多个存储器访问请求的存储器访问请求的就绪状态信息，并且请求执行存储器访问请求 响应就绪状态信息。

    IMPROVED ECC CONFIGURATION IN MEMORIES
    80.
    发明公开
    IMPROVED ECC CONFIGURATION IN MEMORIES 审中-公开

    公开(公告)号：US20240211347A1

    公开(公告)日：2024-06-27

    申请号：US17802053

    申请日：2021-09-23

    Applicant: Micron Technology, Inc.

    Inventor： Graziano Mirichigni ,  Christophe Laurent ,  Riccardo Muzzetto

    IPC: G06F11/10

    CPC classification number: G06F11/1076

    Abstract: The present disclosure relates to a method for operating an array of memory cells, the method comprising storing user data in a plurality of memory cells of the array, storing parity data associated with the user data in a plurality of parity cells of the array, and, based on the stored parity data, selecting an Error Correction Code (ECC) correction capability and/or an ECC granularity according to which an ECC operation is to be performed, wherein the selection of the ECC correction capability and/or the ECC granularity is determined by the steps of updating a first register, said first register comprising values which indicate a required ECC correction capability and/or a required ECC granularity to be applied to the memory cells based on a current status of said memory cells, wherein the values of the first register are updated based on a variation of the current status of the memory cells, and wherein an update of the values of the first register corresponds to a variation of the required ECC correction capability and/or a required ECC granularity to be applied to said memory cells, and based on the updated values of the first register, executing an ECC switch command, wherein the ECC switch command is such as to vary a previously selected ECC correction capability and/or a previously selected ECC granularity, the method further comprising: updating a second register according to the varied ECC correction capability and/or ECC granularity, said second register comprising values indicating the selected ECC correction capability and the selected ECC granularity applied to the memory cells based on the current status thereof. Related apparatuses and systems are also herein disclosed.

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