公开(公告)号：US07820552B2

公开(公告)日：2010-10-26

申请号：US11685558

申请日：2007-03-13

申请人： Siva Kanakasabapathy ,  Ying Zhang ,  Edmund M. Sikorski ,  Hongwen Yan ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Bruce B. Doris

发明人： Siva Kanakasabapathy ,  Ying Zhang ,  Edmund M. Sikorski ,  Hongwen Yan ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Bruce B. Doris

IPC分类号： H01L21/302

CPC分类号： H01L21/31111 ,  H01L21/28088 ,  H01L21/31144 ,  H01L21/31645 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/045 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： An advanced method of patterning a gate stack including a high-k gate dielectric that is capped with a high-k gate dielectric capping layer such as, for example, a rare earth metal (or rare earth like)-containing layer is provided. In particular, the present invention provides a method in which a combination of wet and dry etching is used in patterning such gate stacks which substantially reduces the amount of remnant high-k gate dielectric capping material remaining on the surface of a semiconductor substrate to a value that is less than 1010 atoms/cm2, preferably less than about 109 atoms/cm2.

摘要翻译： 提供了一种构图栅极堆叠的先进方法，该栅极堆叠包括用例如含有稀土金属（或稀土类））层的高k栅介质覆盖层封盖的高k栅极电介质。 特别地，本发明提供了一种方法，其中使用湿蚀刻和干蚀刻的组合来构图这样的栅极堆叠，其将残留在半导体衬底的表面上的剩余的高k栅极电介质封盖材料的量基本上减小到值 小于10 10原子/ cm 2，优选小于约10 9原子/ cm 2。

公开(公告)号：US20080299730A1

公开(公告)日：2008-12-04

申请号：US12190129

申请日：2008-08-12

申请人： Alessandro C. Callegari ,  Michael A. Gribelyuk ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Sufi Zafar

发明人： Alessandro C. Callegari ,  Michael A. Gribelyuk ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Sufi Zafar

IPC分类号： H01L21/336 ,  C23C14/34

CPC分类号： H01L21/28088 ,  H01L21/823828 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A compound metal comprising MOxNy which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the MOxNy compound metal. Furthermore, the MOxNy metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 Å in a p-metal oxide semiconductor (pMOS) device. In the above formula, M is a metal selected from Group IVB, VB, VIB or VIIB of the Periodic Table of Elements, x is from about 5 to about 40 atomic % and y is from about 5 to about 40 atomic %.

摘要翻译： 包含MoxNy的复合金属是具有在包括高k电介质和界面层的栅叠层上热稳定的功函数为约4.75至约5.3，优选约5e的功函数的p型金属，以及 制造MOxNy复合金属的方法。 此外，本发明的MOxNy金属化合物在1000℃下是非常有效的氧扩散阻挡层，允许在p金属氧化物半导体（pMOS）器件中非常有侵蚀性的等效氧化物厚度（EOT）和低于14的反型层厚度标度 。 在上式中，M是选自元素周期表第IVB，VB，VIB或VIIB族的金属，x为约5至约40原子％，y为约5至约40原子％。

公开(公告)号：US07436034B2

公开(公告)日：2008-10-14

申请号：US11311455

申请日：2005-12-19

申请人： Alessandro C. Callegari ,  Michael A. Gribelyuk ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Sufi Zafar

发明人： Alessandro C. Callegari ,  Michael A. Gribelyuk ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Sufi Zafar

IPC分类号： H01L21/00

CPC分类号： H01L21/28088 ,  H01L21/823828 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A compound metal comprising MOxNy which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the MOxNy compound metal. Furthermore, the MOxNy metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 Å in a p-metal oxide semiconductor (PMOS) device. In the above formula, M is a metal selected from Group IVB, VB, VIB or VIIB of the Periodic Table of Elements, x is from about 5 to about 40 atomic % and y is from about 5 to about 40 atomic %.

摘要翻译： 一种复合金属，其包含具有约4.75至约5.3，优选约5eV的功函数的p型金属，其在一个或多个金属上是热稳定的 提供了包括高k电介质和界面层的栅极叠层以及制造复合金属的方法。 此外，本发明的金属氧化物金属化合物在1000℃下是非常有效的氧扩散阻挡层，允许非常有效的等效氧化物厚度（EOT）和反演 在p-金属氧化物半导体（PMOS）器件中的层厚度缩小到14埃以下。 在上式中，M是选自元素周期表第IVB，VB，VIB或VIIB族的金属，x为约5至约40原子％，y为约5至约40原子％。

公开(公告)号：US20080182389A1

公开(公告)日：2008-07-31

申请号：US12062972

申请日：2008-04-04

申请人： Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Paul C. Jamison ,  Rajarao Jammy ,  Barry P. Linder ,  Vijay Narayanan

发明人： Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Paul C. Jamison ,  Rajarao Jammy ,  Barry P. Linder ,  Vijay Narayanan

IPC分类号： H01L21/479

CPC分类号： H01L29/513 ,  H01L21/28194 ,  H01L21/28238 ,  H01L21/823807 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiO2 and a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.

摘要翻译： 一种半导体结构，特别是pFET，其包括介电常数大于SiO 2的介电常数和大于50％的Ge或Si含量的至少一种其它装置， 提供材料堆栈工程的阈值/平带电压调谐。 本发明中考虑的其它方法包括例如在用于电荷固定的电介质的顶部和/或通过形成工程化的沟道区域之间使用绝缘夹层。 本发明还涉及一种制造这种CMOS结构的方法。

公开(公告)号：US08735243B2

公开(公告)日：2014-05-27

申请号：US11834641

申请日：2007-08-06

申请人： Matthew W. Copel ,  Bruce B. Doris ,  Vijay Narayanan ,  Yun-Yu Wang

发明人： Matthew W. Copel ,  Bruce B. Doris ,  Vijay Narayanan ,  Yun-Yu Wang

IPC分类号： H01L21/8238 ,  H01L21/335 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/51 ,  H01L21/28

CPC分类号： H01L29/513 ,  H01L21/28026 ,  H01L21/28229 ,  H01L21/823857 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7833

摘要： A method for fabricating an FET device is disclosed. The FET device has a gate insulator with a high-k dielectric portion, and a threshold modifying material. The method introduces a stabilizing material into the gate insulator in order to hinder one or more metals from the threshold modifying material to penetrate across the high-k portion of the gate insulator. The introduction of the stabilizing material may involve disposing a stabilizing agent over a layer which contains an oxide of the one or more metals. A stabilizing material may also be incorporated into the high-k dielectric. Application of the method may lead to FET devices with unique gate insulator structures.

摘要翻译： 公开了一种用于制造FET器件的方法。 FET器件具有具有高k电介质部分的栅极绝缘体和阈值修饰材料。 该方法将稳定材料引入栅极绝缘体中，以便阻止来自阈值修饰材料的一种或多种金属穿过栅极绝缘体的高k部分。 稳定材料的引入可以包括在包含一种或多种金属的氧化物的层上设置稳定剂。 稳定材料也可以并入高k电介质中。 该方法的应用可能导致具有独特栅极绝缘体结构的FET器件。

公开(公告)号：US07858500B2

公开(公告)日：2010-12-28

申请号：US12062972

申请日：2008-04-04

申请人： Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Paul C. Jamison ,  Rajarao Jammy ,  Barry P. Linder ,  Vijay Narayanan

发明人： Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Paul C. Jamison ,  Rajarao Jammy ,  Barry P. Linder ,  Vijay Narayanan

IPC分类号： H01L21/479

CPC分类号： H01L29/513 ,  H01L21/28194 ,  H01L21/28238 ,  H01L21/823807 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiO2 and a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.

摘要翻译： 一种半导体结构，特别是pFET，其包括具有大于SiO 2的介电常数和大于50％的Ge或Si含量的介电材料和至少一种用于通过材料堆的阈值/平带电压调谐的其它装置 提供工程。 本发明中考虑的其它方法包括例如在用于电荷固定的电介质的顶部和/或通过形成工程化的沟道区域之间使用绝缘夹层。 本发明还涉及一种制造这种CMOS结构的方法。

公开(公告)号：US07923743B2

公开(公告)日：2011-04-12

申请号：US12620629

申请日：2009-11-18

申请人： Nestor Alexander Bojarczuk, Jr. ,  Douglas Andrew Buchanan ,  Supratik Guha ,  Vijay Narayanan ,  Lars-Ake Ragnarsson

发明人： Nestor Alexander Bojarczuk, Jr. ,  Douglas Andrew Buchanan ,  Supratik Guha ,  Vijay Narayanan ,  Lars-Ake Ragnarsson

IPC分类号： H01L29/06 ,  H01L33/00 ,  H01L27/15 ,  H01L31/12

CPC分类号： H01L21/02192 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/02293 ,  H01L21/31604

摘要： A method (and resultant structure) of forming a semiconductor structure, includes forming a mixed rare earth oxide on silicon. The mixed rare earth oxide is lattice-matched to silicon.

摘要翻译： 形成半导体结构的方法（和结果）包括在硅上形成混合的稀土氧化物。 混合的稀土氧化物与硅晶格匹配。

公开(公告)号：US20080311745A1

公开(公告)日：2008-12-18

申请号：US12197845

申请日：2008-08-25

申请人： Ricky Amos ,  Douglas A. Buchanan ,  Cyril Cabral, JR. ,  Alessandro C. Callegari ,  Supratik Guha ,  Hyungjun Kim ,  Fenton R. McFeely ,  Vijay Narayanan ,  Kenneth P. Rodbell ,  John J. Yurkas

发明人： Ricky Amos ,  Douglas A. Buchanan ,  Cyril Cabral, JR. ,  Alessandro C. Callegari ,  Supratik Guha ,  Hyungjun Kim ,  Fenton R. McFeely ,  Vijay Narayanan ,  Kenneth P. Rodbell ,  John J. Yurkas

IPC分类号： H01L21/44

CPC分类号： H01L29/495 ,  H01L21/28079 ,  H01L21/3003

摘要： A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO2, Al2O3 and other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000° C. A low temperature/low pressure CVD technique with Re2(CO)10 as the source material is used when Re is to be deposited.

摘要翻译： 描述了通过使用Re，Rh，Pt，Ir或Ru金属制造CMOS栅电极的方法和包含这种栅电极的CMOS结构。 这些金属的工作功能使其与当前的pFET要求兼容。 例如，金属可以承受生产适当钝化界面而不经历化学变化所需的高氢气压力。 金属在介电层上的热稳定性如SiO 2，Al 2 O 3和其它合适的介电材料使其与后处理温度高达1000℃相兼容。具有Re2（CO）10作为源的低温/低压CVD技术 当Re沉积时使用材料。

公开(公告)号：US07432550B2

公开(公告)日：2008-10-07

申请号：US10998840

申请日：2004-11-30

申请人： Nestor Alexander Bojarczuk, Jr. ,  Douglas Andrew Buchanan ,  Supratik Guha ,  Vijay Narayanan ,  Lars-Ake Ragnarsson

发明人： Nestor Alexander Bojarczuk, Jr. ,  Douglas Andrew Buchanan ,  Supratik Guha ,  Vijay Narayanan ,  Lars-Ake Ragnarsson

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/06 ,  H01L31/0328

CPC分类号： H01L21/02192 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/02293 ,  H01L21/31604

摘要： A method (and resultant structure) of forming a semiconductor structure, includes forming a mixed rare earth oxide on silicon. The mixed rare earth oxide is lattice-matched to silicon.

摘要翻译： 形成半导体结构的方法（和结果）包括在硅上形成混合的稀土氧化物。 混合的稀土氧化物与硅晶格匹配。

公开(公告)号：US20050258491A1

公开(公告)日：2005-11-24

申请号：US10845719

申请日：2004-05-14

申请人： Nestor Bojarczuk ,  Eduard Cartier ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Vijay Narayanan

发明人： Nestor Bojarczuk ,  Eduard Cartier ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Vijay Narayanan

IPC分类号： H01L21/8234 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786 ,  H01L51/00 ,  H01L51/05

CPC分类号： H01L21/28202 ,  H01L21/28194 ,  H01L21/823857 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： An insulating interlayer for use in complementary metal oxide semiconductor (CMOS) that prevents unwanted shifts in threshold voltage and flatband voltage is provided. The insulating interlayer is located between a gate dielectric having a dielectric constant of greater than 4.0 and a Si-containing gate conductor. The insulating interlayer of the present invention is any metal nitride, that optionally may include oxygen, that is capable of stabilizing the threshold and flatband voltages. In a preferred embodiment, the insulating interlayer is aluminum nitride or aluminum oxynitride and the gate dielectric is hafnium oxide, hafnium silicate or hafnium silicon oxynitride. The present invention is particularly useful in stabilizing the threshold and flatband voltage of p-type field effect transistors.

摘要翻译： 提供了用于防止阈值电压和平带电压的不期望的偏移的互补金属氧化物半导体（CMOS）中的绝缘夹层。 绝缘中间层位于介电常数大于4.0的栅极电介质和含Si的栅极导体之间​​。 本发明的绝缘中间层是能够稳定阈值和平带电压的任何金属氮化物，其可任选地包括氧。 在优选实施例中，绝缘中间层为氮化铝或氮氧化铝，栅极电介质为氧化铪，硅酸铪或铪硅氮氧化物。 本发明在稳定p型场效应晶体管的阈值和平带电压方面特别有用。