公开(公告)号：US20060017066A1

公开(公告)日：2006-01-26

申请号：US11231385

申请日：2005-09-21

申请人： Peter Geiss ,  Marwan Khater ,  Qizhi Liu ,  Randy Mann ,  Robert Purtell ,  BethAnn Rainey ,  Jae-Sung Rieh ,  Andreas Stricker

发明人： Peter Geiss ,  Marwan Khater ,  Qizhi Liu ,  Randy Mann ,  Robert Purtell ,  BethAnn Rainey ,  Jae-Sung Rieh ,  Andreas Stricker

IPC分类号： H01L31/109

CPC分类号： H01L29/66242 ,  H01L21/28518 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0804 ,  H01L29/456 ,  H01L29/7371

摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.

摘要翻译： 提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。 在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。 本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。 凸起的外基极上面的硅化物以自对准的方式延伸到发射极。 发射极通过间隔物与硅化物分离。

公开(公告)号：US06809024B1

公开(公告)日：2004-10-26

申请号：US10249821

申请日：2003-05-09

申请人： James S. Dunn ,  Natalie B. Feilchenfeld ,  Qizhi Liu ,  Andreas D. Stricker

发明人： James S. Dunn ,  Natalie B. Feilchenfeld ,  Qizhi Liu ,  Andreas D. Stricker

IPC分类号： H01L2972

CPC分类号： H01L29/66242 ,  H01L21/8249 ,  H01L29/7378

摘要： A method of forming a quasi-self-aligned heterojunction bipolar transistor (HBT) that exhibits high-performance is provided. The method includes the use of a patterned emitter landing pad stack which serves to improve the alignment for the emitter-opening lithography and as an etch stop layer for the emitter opening etch. The present invention also provides an HBT that includes a raised extrinsic base having monocrystalline regions located beneath the emitter landing pad stack.

公开(公告)号：US06239026B1

公开(公告)日：2001-05-29

申请号：US09162185

申请日：1998-09-28

申请人： Qizhi Liu ,  David Feiler

发明人： Qizhi Liu ,  David Feiler

IPC分类号： H01L214763

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76829 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to the reduction of poisoned vias in a submicron process technology semiconductor wafer by reducing the occurrence of over-etched vias through the inclusion of an etch-stop layer. Vias are created to connect conductive portions of a semiconductor wafer and if the vias are over-etched, the connection may be poor. In order to prevent the over-etching of vias, a three-step etch process is completed on a semiconductor wafer having an insulating layer, an etch-stop layer, a low dielectric constant layer, a conductive layer and a foundation layer. A via is first non-selectively etched such that the etch terminates within the insulating layer. The via is subsequently selectively etched such that the etch terminates at the etch-stop layer. Lastly, the via is again non-selectively etched through the etch-stop layer and the low dielectric constant layer such that the etch terminates at the conductive layer.

摘要翻译： 本发明涉及通过减少通过包括蚀刻停止层的过蚀刻通孔的发生来减少亚微米工艺技术半导体晶片中的中毒过孔。 创建通孔以连接半导体晶片的导电部分，并且如果过孔被过蚀刻，则连接可能很差。 为了防止过孔的过度蚀刻，在具有绝缘层，蚀刻停止层，低介电常数层，导电层和基底层的半导体晶片上完成三步蚀刻工艺。 通孔首先被非选择性蚀刻，使得蚀刻终止于绝缘层内。 随后选择性地蚀刻通孔，使得蚀刻终止于蚀刻停止层。 最后，通过蚀刻停止层和低介电常数层再次无选择地蚀刻通孔，使得蚀刻终止于导电层。

公开(公告)号：US08927357B2

公开(公告)日：2015-01-06

申请号：US13294731

申请日：2011-11-11

申请人： Kevin K. Chan ,  John J. Ellis-Monaghan ,  David L. Harame ,  Qizhi Liu ,  John J. Pekarik

发明人： Kevin K. Chan ,  John J. Ellis-Monaghan ,  David L. Harame ,  Qizhi Liu ,  John J. Pekarik

IPC分类号： H01L21/337 ,  H01L29/10 ,  H01L27/06 ,  H01L29/66 ,  H01L29/737 ,  H01L29/808 ,  H01L29/165 ,  H01L29/08

CPC分类号： H01L29/8086 ,  G06F17/5045 ,  H01L27/0623 ,  H01L29/0817 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/1058 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/7375 ,  H01L29/808

摘要： Junction field-effect transistors, methods for fabricating junction field-effect transistors, and design structures for a junction field-effect transistor. A source and a drain of the junction field-effect transistor are comprised of a semiconductor material grown by selective epitaxy and in direct contact with a top surface of a semiconductor layer. A gate is formed that is aligned with a channel laterally disposed in the semiconductor layer between the source and the drain. The source, the drain, and the semiconductor layer are each comprised of a second semiconductor material having an opposite conductivity type from a first semiconductor material comprising the gate.

摘要翻译： 结型场效应晶体管，用于制造结型场效应晶体管的方法，以及结型场效应晶体管的设计结构。 结场效应晶体管的源极和漏极由通过选择性外延生长并与半导体层的顶表面直接接触的半导体材料组成。 形成与在源极和漏极之间横向设置在半导体层中的沟道对准的栅极。 源极，漏极和半导体层各自包括与包括栅极的第一半导体材料具有相反导电类型的第二半导体材料。

公开(公告)号：US08912574B2

公开(公告)日：2014-12-16

申请号：US12967771

申请日：2010-12-14

申请人： Mattias E. Dahlstrom ,  Dinh Dang ,  Qizhi Liu ,  Ramana M. Malladi

发明人： Mattias E. Dahlstrom ,  Dinh Dang ,  Qizhi Liu ,  Ramana M. Malladi

IPC分类号： H01L21/763 ,  H01L23/367 ,  H01L21/762 ,  H01L29/08 ,  H01L29/66 ,  H01L29/737

CPC分类号： H01L29/66242 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/763 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/373 ,  H01L29/0821 ,  H01L29/7371 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of making a semiconductor structure includes forming a trench through a shallow trench isolation (STI) structure and into a substrate, and forming a liner including an electrical insulator material on sidewalls of the trench. The method also includes forming a core including a high thermal conductivity material in the trench and on the liner, and forming a cap in the trench and on the core.

摘要翻译： 制造半导体结构的方法包括通过浅沟槽隔离（STI）结构形成沟槽并且形成衬底，以及在沟槽的侧壁上形成包括电绝缘体材料的衬垫。 该方法还包括在沟槽和衬垫上形成包括高导热性材料的芯，并在沟槽和芯上形成帽。

公开(公告)号：US20130214275A1

公开(公告)日：2013-08-22

申请号：US13401064

申请日：2012-02-21

申请人： James W. Adkisson ,  David L. Harame ,  Qizhi Liu

发明人： James W. Adkisson ,  David L. Harame ,  Qizhi Liu

IPC分类号： H01L29/737 ,  H01L21/331

CPC分类号： H01L29/732 ,  H01L29/1004 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/7371

摘要： Disclosed are a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a narrow in-substrate collector region for reduced base-collector junction capacitance. The transistor has, within a substrate, a collector region positioned laterally adjacent to a trench isolation region. A relatively thin seed layer covers the trench isolation region and collector region. This seed layer has a monocrystalline center, which is aligned above and wider than the collector region (e.g., due to a solid phase epitaxy regrowth process), and a polycrystalline outer section. An intrinsic base layer is epitaxially deposited on the seed layer such that it similarly has a monocrystalline center section that is aligned above and wider than the collector region. An extrinsic base layer is the intrinsic base layer and has a monocrystalline extrinsic base-to-intrinsic base link-up region that is offset vertically from the collector region.

摘要翻译： 公开了晶体管（例如，双极结型晶体管（BJT）或异质结双极晶体管（HBT））以及形成具有窄的衬底内集电极区域以减小基极 - 集电极结电容的晶体管的方法。 晶体管在衬底内具有位于横向邻近沟槽隔离区域的集电极区域。 相对薄的种子层覆盖沟槽隔离区域和收集器区域。 该晶种层具有单晶中心，该晶体中心在集电极区域上方（例如由于固相外延再生长工艺）而上方且更宽，并且多晶外部部分。 本征基底层外延沉积在种子层上，使得其类似地具有在集电极区域上方并且更宽的单晶中心部分。 非本征基层是本征基层，并且具有从集电极垂直偏移的单晶非本征基本至本征基极连接区域。

公开(公告)号：US20130126944A1

公开(公告)日：2013-05-23

申请号：US13303248

申请日：2011-11-23

申请人： Thomas N. Adam ,  David L. Harame ,  Qizhi Liu ,  Alexander Reznicek

发明人： Thomas N. Adam ,  David L. Harame ,  Qizhi Liu ,  Alexander Reznicek

IPC分类号： H01L29/70 ,  H01L21/331

CPC分类号： H01L21/0262 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/66242 ,  H01L29/7371

摘要： A heterojunction bipolar transistor (HBT) may include an n-type doped crystalline collector formed in an upper portion of a crystalline silicon substrate layer; a p-type doped crystalline p+Si1-xGex layer, formed above the n-type doped collector, that forms a p-type doped internal base of the HBT; a crystalline silicon cap formed on the p-type doped crystalline p+Si1-xGex layer, in which the crystalline silicon cap includes an n-type impurity and forms an n-type doped emitter of the HBT; and an n-type doped crystalline silicon emitter stack formed within an opening through an insulating layer to an upper surface of the crystalline silicon cap.

摘要翻译： 异质结双极晶体管（HBT）可以包括在晶体硅衬底层的上部形成的n型掺杂晶体集电极; 形成在n型掺杂集电极上方的p型掺杂晶体p + Si1-xGex层，其形成HBT的p型掺杂内部基极; 形成在p型掺杂结晶p + Si1-xGex层上的晶体硅帽，其中晶体硅帽包括n型杂质并形成HBT的n型掺杂发射极; 以及形成在通过绝缘层的开口内的晶体硅帽的上表面的n型掺杂晶体硅发射极堆叠。

公开(公告)号：US20130119436A1

公开(公告)日：2013-05-16

申请号：US13297464

申请日：2011-11-16

申请人： Kevin K. Chan ,  Peng Cheng ,  Qizhi Liu ,  Ljubo Radic

发明人： Kevin K. Chan ,  Peng Cheng ,  Qizhi Liu ,  Ljubo Radic

IPC分类号： H01L29/737 ,  G06F17/50 ,  H01L21/331

CPC分类号： H01L29/73 ,  G06F17/5045 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/7371

摘要： Methods of fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. A first portion of the intrinsic base layer is masked while a second portion of an intrinsic base layer is etched. As a consequence of the masking, the second portion of the intrinsic base layer is thinner than the first portion of the intrinsic base layer. An emitter and an extrinsic base layer are formed in respective contacting relationships with the first and second portions of the intrinsic base layer.

公开(公告)号：US08415763B2

公开(公告)日：2013-04-09

申请号：US13076781

申请日：2011-03-31

申请人： David Louis Harame ,  Alvin Jose Joseph ,  Qizhi Liu ,  Ramana Murty Malladi

发明人： David Louis Harame ,  Alvin Jose Joseph ,  Qizhi Liu ,  Ramana Murty Malladi

IPC分类号： H01L29/66

CPC分类号： H01L29/73 ,  H01L29/0821 ,  H01L29/66272 ,  H01L29/732

摘要： Embodiments of the invention include a method for forming a tunable semiconductor device and the resulting structure. The invention comprises forming a semiconductor substrate. Next, pattern a first mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the first mask to form a first discontinuous subcollector. Remove the first mask. Pattern a second mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the second mask and on top of the first discontinuous subcollector to form a second discontinuous subcollector. Remove the second mask and form a collector above the second discontinuous subcollector. Breakdown voltage of the device may be tuned by varying the gaps separating doped regions within the first and second discontinuous subcollectors. Doped regions of the first and second discontinuous subcollectors may be formed in a mesh pattern.

摘要翻译： 本发明的实施例包括形成可调谐半导体器件的方法和所得到的结构。 本发明包括形成半导体衬底。 接下来，在半导体衬底上形成第一掩模。 半导体衬底的掺杂区域不被第一掩模保护以形成第一不连续子集电极。 删除第一个面具。 在半导体衬底上形成第二掩模。 半导体衬底的掺杂区域不被第二掩模保护，并且在第一不连续子集电极的顶部上形成第二不连续子集电极。 取下第二个掩模，并在第二个不连续的子集电极上形成集电极。 可以通过改变分离第一和第二不连续子集电极内的掺杂区域的间隙来调谐器件的击穿电压。 可以以网格图案形成第一和第二不连续子集电极的掺杂区域。

公开(公告)号：US20120248573A1

公开(公告)日：2012-10-04

申请号：US13076781

申请日：2011-03-31

申请人： David Louis Harame ,  Alvin Jose Joseph ,  Qizhi Liu ,  Ramana Murty Malladi

发明人： David Louis Harame ,  Alvin Jose Joseph ,  Qizhi Liu ,  Ramana Murty Malladi

IPC分类号： H01L29/70

CPC分类号： H01L29/73 ,  H01L29/0821 ,  H01L29/66272 ,  H01L29/732

摘要： Embodiments of the invention include a method for forming a tunable semiconductor device and the resulting structure. The invention comprises forming a semiconductor substrate. Next, pattern a first mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the first mask to form a first discontinuous subcollector. Remove the first mask. Pattern a second mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the second mask and on top of the first discontinuous subcollector to form a second discontinuous subcollector. Remove the second mask and form a collector above the second discontinuous subcollector. Breakdown voltage of the device may be tuned by varying the gaps separating doped regions within the first and second discontinuous subcollectors. Doped regions of the first and second discontinuous subcollectors may be formed in a mesh pattern.

摘要翻译： 本发明的实施例包括形成可调谐半导体器件的方法和所得到的结构。 本发明包括形成半导体衬底。 接下来，在半导体衬底上形成第一掩模。 半导体衬底的掺杂区域不被第一掩模保护以形成第一不连续子集电极。 删除第一个面具。 在半导体衬底上形成第二掩模。 半导体衬底的掺杂区域不被第二掩模保护，并且在第一不连续子集电极的顶部上形成第二不连续子集电极。 取下第二个掩模，并在第二个不连续的子集电极上形成集电极。 可以通过改变分离第一和第二不连续子集电极内的掺杂区域的间隙来调谐器件的击穿电压。 可以以网格图案形成第一和第二不连续子集电极的掺杂区域。